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A3966

Dual Full-Bridge PWM Motor Driver

Allegro MicroSystems 

A3966

Dual Full-Bridge PWM Motor Driver

FUNCTIONAL DESCRIPTION (continued)

Load Current Regulation. Due to internal logic and

switching delays, td , the actual load current peak will be

slightly higher than the ITRIP value. These delays, plus the

blanking time, limit the minimum value the current control

circuitry can regulate. To produce zero current in a wind-

ing, the ENABLE terminal should be held high, turning off

all output drivers for that full-bridge.

Logic Inputs. A logic high on the PHASE input results

in current flowing from OUTA to OUTB of that full-bridge.

A logic low on the PHASE input results in current flowing

from OUTB to OUTA. An internally generated dead time,

tcodt , of approximately 1 μs prevents crossover-current

spikes that can occur when switching the PHASE input.

A logic high on the ENABLE input turns off all four

output drivers of that full-bridge. This results in a fast cur-

rent decay through the internal ground clamp and flyback

diodes. A logic low on the ENABLE input turns on the

selected source and sink driver of that full-bridge.

The ENABLE inputs can be pulse-width modulated

for applications that require a fast current-decay PWM. If

external current-sensing circuitry is used, the internal cur-

rent-control logic can be disabled by connecting the RTCT

terminal to ground.

The REFERENCE input voltage is typically set with a

resistor divider from VCC. This reference voltage is inter-

nally divided down by 4 to set up the current-comparator

trip-voltage threshold. The reference input voltage range is

0 to 2 V.

Output Drivers. To minimize on-chip power dissipa-

tion, the sink drivers incorporate a Satlington structure.

The Satlington output combines the low VCE(sat) features

of a saturated transistor and the high peak-current capabil-

ity of a Darlington (connected) transistor. A graph showing

typical output saturation voltages as a function of output

current is on page 5.

Miscellaneous Information. Thermal protection

circuitry turns off all output drivers should the junction

temperature reach 165 °C typical. This is intended only to

protect the device from failures due to excessive junction

temperatures and should not imply that output short circuits

are permitted. Normal operation is resumed when the junc-

tion temperature has decreased about 15°C.

The A3966 current control employs a fixed-frequency,

variable duty cycle PWM technique. As a result, the cur-

rent-control regulation may become unstable if the duty

cycle exceeds 50%.

To minimize current-sensing inaccuracies caused by

ground trace IR drops, each current-sensing resistor should

have a separate return to the ground terminal of the device.

For low-value sense resistors, the I x R drops in the printed-

wiring board can be significant and should be taken into ac-

count. The use of sockets should be avoided as their contact

resistance can cause variations in the effective value of RS.

The LOAD SUPPLY terminal, VBB, should be decou-

pled with an electrolytic capacitor (47 μF recommended)

placed as close to the device as physically practical. To

minimize the effect of system ground I x R drops on the

logic and reference input signals, the system ground should

have a low-resistance return to the load supply voltage.

The frequency of the clock oscillator will determine the

amount of ripple current. A lower frequency will result in

higher current ripple, but reduced heating in the motor and

driver IC due to a corresponding decrease in hysteretic core

losses and switching losses respectively. A higher frequen-

cy will reduce ripple current, but will increase switching

losses and EMI.

Allegro MicroSystems, LLC

7

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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