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A3966

Dual Full-Bridge PWM Motor Driver

Allegro MicroSystems 

A3966

Dual Full-Bridge PWM Motor Driver

FUNCTIONAL DESCRIPTION

Internal PWM Current Control. The A3966 dual full-

bridges are designed to drive both windings of a bipolar

stepper motor. Load current can be controlled in each motor

winding by an internal fixed-frequency PWM control cir-

cuit. The current-control circuitry works as follows: when

the outputs of the full-bridge are turned on, current increas-

es in the motor winding. The load current is sensed by the

current-control comparator via an external sense resistor

(RS). Load current continues to increase until it reaches

the predetermined value, set by the selection of external

current-sensing resistors and reference input voltage (VREF)

according to the equation:

ITRIP = IOUT + ISO = VREF/(4 RS)

where ISO is the sense-current error (typically 18 mA) due

to the base-drive current of the sink driver transistor.

At the trip point, the comparator resets the source-en-

able latch, turning off the source driver of that full-bridge.

The source turn-off of one full-bridge is independent of

the other full-bridge. Load inductance causes the current to

recirculate through the sink driver and ground-clamp diode.

The current decreases until the internal clock oscillator sets

the source-enable latches of both Full-bridges, turning on

the source drivers of both bridges. Load current increases

again, and the cycle is repeated.

The frequency of the internal clock oscillator is set by

the external timing components RTCT. The frequency can

be approximately calculated as:

fosc = 1/(RT CT + tblank)

where tblank is defined below.

The range of recommended values for RT and CT are

20 to 100 k and 470 to 1000 pF respectively. Nominal

values of 56 k and 680 pF result in a clock frequency of

25 kHz.

Current-Sense Comparator Blanking. When the

source driver is turned on, a current spike occurs due to the

reverse-recovery currents of the clamp diodes and switch-

ing transients related to distributed capacitance in the load.

To prevent this current spike from erroneously resetting the

source enable latch, the current-control comparator output

is blanked for a short period of time when the source driver

is turned on. The blanking time is set by the timing compo-

nent CT according to the equation:

tblank = 1900 CT (μs).

A nominal CT value of 680 pF will give a blanking time

of 1.3 μs.

The current-control comparator is also blanked when

the Full-bridge outputs are switched by the PHASE or

ENABLE inputs. This internally generated blank time is

approximately 1 μs.

V PHASE

+

I OUT 0

–

BRIDGE

ON

See Enlargement A

ALL

OFF

BRIDGE

ON

Enlargement A

INTERNAL

OSCILLATOR

I TRIP

td

RTCT

SOURCE

OFF

tblank

Dwg. WM-003-2

V

BB

BRIDGE ON

SOURCE OFF

ALL OFF

RS

Dwg. EP-006-16

Allegro MicroSystems, LLC

6

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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