93LCS56 데이터 시트보기 (PDF) - Microchip Technology
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93LCS56 Datasheet PDF : 12 Pages
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FIGURE 2-4: EWDS TIMING
CS
CLK
93LCS56/66
TCSL
DI
1
0
0
0
0
X
•••
X
FIGURE 2-5: WRITE TIMING
PE
6 DON'T CARE BITS
CS
TCSL
PRE = 0
PE = X
DO = TRI-STATE
CLK
DI
1
0
1
A7 • • • A0 D15 • • • D0
TRI-STATE
DO
• Address bit A7 becomes a "don't care" for 93LCS56.
FIGURE 2-6: WRAL TIMING
PRE = 0
PE
CS
BUSY
TWC
TCSL
READY
CLK
DI
1
0
0
0
1
X
•••
X D15 • • • D0
DO
TRI-STATE
Guaranteed at VCC = 4.5V to 6.0V
Protect Register must be cleared PRE = 0
6 DON'T CARE BITS
BUSY READY TRISTATE
TWL
© 1996 Microchip Technology Inc.
Preliminary
DS11181D-page 7
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