93LCS56 데이터 시트보기 (PDF) - Microchip Technology
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93LCS56 Datasheet PDF : 12 Pages
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93LCS56/66
FIGURE 2-1: SYNCHRONOUS DATA TIMING
VIH
PRE
VIL
TPRES
PE VIH
VIL
TPES
VIH
CS
VIL
TCSS
TCKH
TCKL
VIH
CLK
VIL
VIH
DI
VIL
TDIS
DO VOH
(READ) VOL
TSV
DO VOH
(PROGRAM)
VOL
TDIH
TPD
TPD
STATUS VALID
FIGURE 2-2: READ TIMING
CS
CLK
DI
1
1
0
A2 • • • A0
TPREH
TPEH
TCSH
TCZ
TCZ
TCSL
DO
TRI-STATE®
0
D15 • • • D0 D15* • • • D0 D15* • • •
PRE = 0
* The memory automatically cycles to the next register.
PE = X
Tri-State is a registered trademark of National Semiconductor.
FIGURE 2-3: EWEN TIMING
PE
CS
TCSL
CLK
DI
DS11181D-page 6
1
0
0
1
1
X
•••
X
6 DON'T CARE BITS
Preliminary
PRE = 0
DO = TRI-STATE
© 1996 Microchip Technology Inc.
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