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74F598

8-bit shift register with input storage registers (3-State)

Philips Electronics

74F598 Datasheet PDF : 14 Pages

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Philips Semiconductors

8-bit shift register with input storage registers (3-State)

Product specification

74F598

FEATURES

• High impedance PNP base input for reduced loading (20µA in

High and Low states)

• 8–bit parallel storage register

• Shift register has asynchronous direct overriding reset

• Shift load SHLD is functional when SHCP is Low and locked out

when SHCP is High.

• Guaranteed shift frequency DC to 105MHz

• Parallel 3–State I/O storage register inputs and shift register

parallel outputs

DESCRIPTION

The 74F598 consists of an 8–bit storage register feeding a

parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both

the storage register and shift register have positive edge–triggered

clocks. The shift register has asynchronous reset and when SHCP

is Low, it has asynchronous load.

The shift register load function has been modified to load when both

SHLD and SHCP are Low. When SHCP is High the shift register

load operation is not performed. Data will be properly shifted on the

rising edge of SHCP when SHLD is High.

TYPE TYPICAL SHCP fmax

74F598

100MHz

TYPICAL SUPPLY

CURRENT (TOTAL)

75mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

20–pin plastic DIP

COMMERCIAL RANGE

VCC = 5V ±10%,

Tamb = 0°C to +70°C

N74F598N

20–pin plastic SOL

N74F598D

PKG DWG #

SOT146-1

SOT163-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

I/On

Parallel data input

Ds0, Ds1 Serial data inputs

SHCP

Shift register clock pulse input

STCP

Storage register clock pulse input

SHCPEN Shift register clock pulse enable input

SHLD

Shift register load input (active Low)

SHRST

Shift register reset input (active Low)

Serial data select input

Output enable input

Serial data output

I/On

Parallel data outputs

Note to input and output loading and fan out table

1. One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

74F (U.L.) High/

Low

1.0/0.033

50/33

150/40

PIN CONFIGURATION

LOGIC SYMBOL

LOAD VALUE

High/Low

20µA/20µA

1.0mA/20mA

3.0mA/24mA

I/O0 1

I/O1 2

I/O2 3

I/O3 4

I/O4 5

I/O5 6

I/O6 7

I/O7 8

SHLD 9

GND 10

20 VCC

19 S

18 DS0

17 DS1

16 OE

15 STCP

14 SHCPEN

13 SHCP

12 SHRST

11 Qs

SF00375

18 17 1 2 3 4 5 6 7 8

Ds0 Ds1 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7

STCP

SHCPEN

SHCP

SHRST

SHLD

VCC = Pin 20

GND = Pin 10

SF00376

1991 Oct 21

853–1583 04407

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