EN29F002(2000) 데이터 시트보기 (PDF) - Eon Silicon Solution Inc.
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EN29F002 Datasheet PDF : 32 Pages
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EN29F002 / EN29F002N
Table 6. Status Register Bits
DQ
Name
Logic Level
Definition
‘1’
Erase Complete or
erase block in Erase suspend
‘0’
Erase On-Going
DATA
7
POLLING
DQ7
Program Complete or
data of non-erase block during
Erase Suspend
DQ7
Program On-Going
‘-1-0-1-0-1-0-1-’ Erase or Program On-going
DQ6
Read during Erase Suspend
TOGGLE
6
BIT
‘-1-1-1-1-1-1-1-‘
Erase Complete
5
ERROR BIT
‘1’
Program or Erase Error
‘0’
Program or Erase On-going
ERASE
‘1’
3
TIME BIT
Erase operation start
‘0’
Erase timeout period on-going
‘-1-0-1-0-1-0-1-’
Chip Erase, Erase or Erase
suspend on currently
addressed
block. (When DQ5=1, Erase
Error due to currently
addressed block. Program
during Erase Suspend on-
going at current address
2
TOGGLE
BIT
DQ2
Erase Suspend read on
non Erase Suspend Block
Notes:
DQ7 DATA Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits
DQ5 for Program or Erase Success.
DQ6 Toggle Bit: remains at constant level when P/E C operations are complete or erase suspend is acknowledged.
Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.
DQ5 Error Bit: set to “1’ if failure in programming or erase
DQ3 P/E C Erase Time Bit: Operation has started. Only possible command is Erase suspend (ES).
DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased block.
DATA PROTECTION
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE = VIL, W E = VIL and OE = VIH, the device will not accept commands on the rising edge of
WE.
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