EN29F002(2000) 데이터 시트보기 (PDF) - Eon Silicon Solution Inc.

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EN29F002
(Rev.:2000)

2 Megabit (256K x 8-bit) Flash Memory

Eon Silicon Solution Inc. 

EN29F002 / EN29F002N

selected blocks are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read

mode without changing data in all protected blocks.

Toggling either CE or OE will cause DQ6 to toggle.

The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is

shown in Figure 9.

DQ5

Exceeded Timing Limits

DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse

count). Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates

that the program or erase cycle was not successfully completed. DATA Polling (DQ7), Toggle Bit

(DQ6) and Erase Toggle Bit (DQ2) still function under this condition. The CE circuit will partially

power down the device under those conditions. The O E and W E pins will control the output disable

functions as described in Table 3.

The DQ5 failure condition will also appear if the user tries to program a “1” to a location that was

previously programmed to a “0”. In this case, the device locks out and never completes the

Embedded Program Algorithm. Hence, the system never reads valid data on DQ7 and DQ6 never

stops toggling. Once the device exceeds the timing limits, DQ5 will indicate a “1”. Please note that

this is not a device failure condition since the device was used incorrectly. If timing limits are

exceeded, reset the device. (See Table 6)

DQ3

Block Erase Timer

After the completion of the initial Block Erase command sequence, the Block Erase time-out window

will begin. DQ3 will remain low until the time-out window is closed. DATA Polling and the Toggle Bit

are valid after the initial Block Erase command sequence. (See Table 6)

If DATA Polling or the Toggle Bit indicates the device has been written with a valid Block Erase

command, DQ3 may be used to determine if the block erase time-out window is still open. If DQ3

returns a “1”, the internally controlled erase cycle has begun.

DQ2

Erase Toggle Bit

In the block erase operation, DQ2 will toggle with OE or CE when a read is attempted within the

block that is being erased. DQ2 will not toggle if the read address is not within the block that is

selected to be erased. In the chip erase operation, however, DQ2 will toggle with OE or CE

regardless of the address given by the user. This is because all blocks are to be erased. (See Table

6)

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