CY7C4221V-25JC 데이터 시트보기 (PDF) - Cypress Semiconductor
부품명
상세내역
일치하는 목록
CY7C4221V-25JC Datasheet PDF : 16 Pages
| |||
CY7C4421V/4201V/4211V/4221V
PRELIMINARY
CY7C4231V/4241V/4251V
Functional Description (continued)
The CY7C42X1V provides four status pins: Empty, Full, Almost
Empty, Almost Full. The Almost Empty/Almost Full flags are program-
mable to single word granularity. The programmable flags default to
Empty−7 and Full−7.
The flags are synchronous, i.e., they change state relative to
either the read clock (RCLK) or the write clock (WCLK). When
entering or exiting the Empty and Almost Empty states, the
flags are updated exclusively by the RCLK. The flags denoting
Almost Full, and Full states are updated exclusively by WCLK.
The synchronous flag architecture guarantees that the flags
maintain their status for at least one cycle
All configurations are fabricated using an advanced 0.65µ
P-Well CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (mA)
Commercial
7C42X1V-15
66.7
11
15
4
1
10
20
7C42X1V-25
40
15
25
6
1
15
20
7C42X1V-35
28.6
20
35
7
2
20
20
Density
CY7C4421V CY7C4201V CY7C4211V CY7C4221V CY7C4231V CY7C4241V CY7C4251V
64 x 9
256 x 9
512 x 9
1K x 9
2K x 9
4K x 9
8K x 9
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ....................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................... −55°C to +125°C
Supply Voltage to Ground Potential .................−0.5V to +5.0V
DC Voltage Applied to Outputs
in High Z State .....................................................−0.5V to +5.0V
DC Input Voltage .................................................−0.5V to +5.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ..................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
VCC
3.3V ± 300mV
Pin Definitions
Signal Name Description
D0 − 8
Q0 − 8
WEN1
Data Inputs
Data Outputs
Write Enable 1
WEN2/LD
Write Enable 2
Dual Mode Pin Load
REN1, REN2
WCLK
Read Enable
Inputs
Write Clock
I/O
Description
I Data Inputs for 9-bit bus
O Data Outputs for 9-bit bus
I The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF is HIGH.
If the FIFO is configured to have two write enables, data is written on a LOW-to-HIGH transition
of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this pin
I
operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into the FIFO
if the FF is LOW. If the FIFO is configured to have programmable flags, WEN2/LD is held LOW
to write or read the programmable flag offsets.
I Enables the device for Read operation.
I The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is HIGH
and the FIFO is not Full. When LD is asserted, WCLK writes data into the programmable flag-off-
set register.
2
Share Link: 