CY7C4221V-25JC 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C4221V-25JC

Low Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

Cypress Semiconductor 

CY7C4421V/4201V/4211V/4221V

PRELIMINARY

CY7C4231V/4241V/4251V

Switching Waveforms (continued)

Programmable Almost Full Flag Timing

tCLKH

tCLKL

WCLK

WEN1

tENS tENH

Note 19

WEN2

(if applicable)

PAF

RCLK

REN1,

REN2

tENS tENH

FULL − M+1 WORDS

IN FIFO

Note 20

tPAF

FULL − M WORDS

IN FIFO [21]

tSKEW2 [22]

tENS

tENS tENH

tPAF

42X1V–13

Write Programmable Registers

tCLKH

tCLK

tCLKL

WCLK

WEN2/LD

tENS

tENH

WEN1

tENS

tDS

tDH

D0 –D8

PAE OFFSET

LSB

PAE OFFSET

MSB

PAF OFFSET

LSB

PAF OFFSET

MSB

42X1V–14

Notes:

19. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.

20. PAF offset = m.

21. 64-m words for CY7C4421V, 256-m words in FIFO for CY7C4201V, 512−m words for CY7C4211V, 1024−m words for CY7C4221V, 2048−m words for

CY7C4231V, 4096−m words for CY7C4241V, 8192-m words for CY7C4251V.

22. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK

and the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK.

10

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