LD39300(2017) 데이터 시트보기 (PDF) - STMicroelectronics

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LD39300
(Rev.:2017)

Ultra low drop BICMOS voltage regulator

STMicroelectronics 

Pin configuration

2

Pin configuration

Figure 2: Pin connections (top view for DPAK and PPAK)

LD39300

Pin N°

PPAK DPAK

Symbol

Table 2: Pin description

Note

VSENSE/N.C. For fixed versions: Not connected on PPAK

5

ADJ

For adjustable version: error amplifier Input pin for VO from 1.22 to 5.0 V

2

1

VI

LDO input voltage; VI from 2.5 V to 6 V, CI = 1 µF must be located at a distance of

not more than 0.5’’ from input pin.

4

3

1

VO

LDO output voltage pins, with minimum CO = 4.7 µF needed for stability (also refer

to CO vs ESR stability chart)

VINH

Inhibit input voltage: ON MODE when VINH ≥ 2 V, OFF MODE when VINH ≤ 0.3 V

(do not leave floating, not internally pulled down/up)

3

2

GND

Common ground

TAB

GND

Tab is connected to GND

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DocID13160 Rev 3

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