MX86250 데이터 시트보기 (PDF) - Macronix International
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MX86250 Datasheet PDF : 25 Pages
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INDEX
MX86250
2.10 Power-on Reset Strapping
MD[3:0]: RASTCTRL[3:0]
These 4 bits are used for RAS precharge/low timing con-
trols. The selection is listed below :
RASTCTRL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
RAS precharge
(in MCLK)
3.5
3.5
3.5
2.5
2.5
2.5
1.5
1.5
3
3
3
2
2
2
Reserved
Reserved
RAS low
(in MCLK)
5.5
4.5
3.5
4.5
3.5
2.5
3.5
2.5
6
5
4
5
4
3
Reserved
Reserved
MD[5:4]: DRAMCYC[1:0]
DRAMCYC[1:0]
00
01
10
11
DRAM CYCLES
2 cycles Fast Page DRAM cycle
2 cycles EDO DRAM cycle
1 cycles EDO DRAM cycle
Reserved
MD10: MA9OUTSE
This is used to select MA9 output pin if UMA is enabled.
0--MA9 output through WEB1
1--MA9 output through OEB
MD11: Reserved
MD12: EXTMCLK
0--Use internal MCLK
1--Use external MCLK. For UMA, external MCLK
will come from CPU clock.
MD13: EXTDCLK
0--Use internal DCLK
1--Use external DCLK
MD14: FC8
0--16-bit or No Feature Connector
1--8-bit Feature Connector
MD15: ENSTVW
0--Stereo View off.
1--Enable Stereo View. DD1 is used for stereo view
control. DD1 is high for odd field, low for even field
during interlaced display.
For non-interlaced display, DD1 is always low.
MD16: RETRYOFF
0--Enable Bus Retry.
1--Disable Bus Retry.
MD17: CROMRETRYOFF
0--Enable disconnect function for Configuration and ROM
accesses.
1--Disable disconnect function for Configuration and ROM
accesses.
MD6: DUALCAS
0--Dual WE DRAM
1--Dual CAS DRAM
MD7: ENUMA
0--Disable UMA
1--Enable UMA
MD8: Reserved
MD9: Reserved
P/N:PM0387
8
REV. 1.1, JUL 26, 1996
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