MX86250 데이터 시트보기 (PDF) - Macronix International

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MX86250

THE ADVANCED 64-BIT WINDOWS-95 AND DIRECTDRAW ACCELERATOR

Macronix International 

INDEX

MX86250

Motion Video Codec Acceleration

Extended Display Resolution support

• YUV/YCrCb conversion of industry standard YUV 4.2.2

or 2.1.1 formats

• Non-integer zoom in both X and Y direction

• Interpolation with Bi-linear filters in both Horizontal and

Vertical dimensions

• Color Key supports video overlay, Chroma key sup

ports transparency effect or blue screen video

• Edge Blending for smooth looking Blue screen video

• Video window is double buffered for smooth video play

back.

• Independent video window mode allowing true-color

video, independent of graphics color depth.

Windows 95 Game acceleration

• Designed to accelerate Windows 95 DirecDraw for

game acceleration

• Fast Transparent BitBLT for sprite animation

• Linear access to offscreen DirectDraw surface storing

multiple sprites

• Double buffer to support page flipping which is syn

chronized to vertical retrace

Media Port interface to MPEG decoder chips or

Video Capture frontend

• Glueless interface to VMI (Video Module Interface)

connector to allow plug-in daughtercard of hardware

MPEG-1 support

• Glueless interface to Phillips 7110 for live video input

• Dual aperture for simultaneous access to display

memory from Graphics and Video

• Built in FIFO and flexible decimator

• 1600x1200, 64K color (int)

• 1280x1024, 64K color @ 75 Hz

• 1024x768, 16M color @ 60 Hz

"Green PC"” power management

• Support VESA DPMS (Display Power Management)

standard

• Built in advanced power management techniques such

as internal DAC power down mode and clock

idle modes

Multiple peripheral interfaces

• VESA Display Data Channel (DDC-2B) protocol

support

• Two wire EEPROM interface

• I2C channel

• VESA standard and advanced Feature Connector

(VAFC) Support

• General purpose I/O pins

Complete Hardware compatibility

• Windows 95 Plug and Play compliant

• VGA Hardware, register, and BIOS compatible

• PCI revision 2.1 compatible

Low-Power 0.5 um CMOS technology

208 pin PQFP package

High speed PCI local bus

• Support zero wait state PCI burst cycles for maximum

CPU write bandwidth

• Support version 2.1 PCI disconnect and retry cycles

to free CPU from status polling overhead

• level command and data FIFO

Unified Memory Architecture (UMA) support

• Support VESA UMA (VUMA) standard

• Programmable wait states in DRAM access cycles to

work with slower main memory DRAM chips

• DRAM interface buffers have programmable drive

strength for optimal power versus performance tradeoff

P/N:PM0387

REV. 1.1, JUL 26, 1996

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