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CS5421

Dual Out−of−Phase Synchronous Buck Controller with Remote Sense

ON Semiconductor 

CS5421

APPLICATIONS INFORMATION

THEORY OF OPERATION

The CS5421 is a dual power supply controller that utilizes

the V2 control method. Two synchronous V2 buck regulators

can be built using a single controller. The fixed−frequency

architecture, driven from a common oscillator, ensures a

180° phase differential between channels.

V2 Control Method

The V2 method of control uses a ramp signal that is

generated by the ESR of the output capacitors. This ramp is

proportional to the AC current through the main inductor

and is offset by the DC output voltage. This control scheme

inherently compensates for variation in either line or load

conditions, since the ramp signal is generated from the

output voltage itself. The V2 method differs from traditional

techniques such as voltage mode control, which generates an

artificial ramp, and current mode control, which generates

a ramp using the inductor current.

PWM

Comparator

−

GATE(H)

+

GATE(L)

COMP

RAMP

VFFB

Slope

Compensation Error

Amplifier −

Error

Signal

+

Output

Voltage

Feedback

VFB

Reference

Voltage

Figure 3. V2 Control with Slope Compensation

The V2 control method is illustrated in Figure 3. The

output voltage generates both the error signal and the ramp

signal. Since the ramp signal is simply the output voltage, it

is affected by any change in the output, regardless of the

origin of that change. The ramp signal also contains the DC

portion of the output voltage, allowing the control circuit to

drive the main switch to 0% or 100% duty cycle as required.

A variation in line voltage changes the current ramp in the

inductor, which causes the V2 control scheme to compensate

the duty cycle. Since any variation in inductor current

modifies the ramp signal, as in current mode control, the V2

control scheme offers the same advantages in line transient

response.

A variation in load current will affect the output voltage,

modifying the ramp signal. A load step immediately changes

the state of the comparator output, which controls the main

switch. The comparator response time and the transition

speed of the main switch determine the load transient

response. Unlike traditional control methods, the reaction

time to the output load step is not related to the crossover

frequency of the error signal loop.

The error signal loop can have a low crossover frequency,

since the transient response is handled by the ramp signal

loop. The main purpose of this ‘slow’ feedback loop is to

provide DC accuracy. Noise immunity is significantly

improved, since the error amplifier bandwidth can be rolled

off at a low frequency. Enhanced noise immunity improves

remote sensing of the output voltage, since the noise

associated with long feedback traces can be effectively

filtered.

Line and load regulation is drastically improved because

there are two independent control loops. A voltage mode

controller relies on the change in the error signal to

compensate for a deviation in either line or load voltage.

This change in the error signal causes the output voltage to

change corresponding to the gain of the error amplifier,

which is normally specified as line and load regulations. A

current mode controller maintains a fixed error signal during

line transients, since the slope of the ramp signal changes in

this case. However, regulation of load transients still requires

a change in the error signal. The V2 method of control

maintains a fixed error signal for both line and load variation,

since the ramp signal is affected by both line and load.

The stringent load transient requirements of modern

microprocessors require the output capacitors to have very

low ESR. The resulting shallow slope in the output ripple

can lead to pulse width jitter and variation caused by both

random and synchronous noise. A ramp waveform

generated in the oscillator is added to the ramp signal from

the output voltage to provide the proper voltage ramp at the

beginning of each switching cycle. This slope compensation

increases the noise immunity particularly at higher duty

cycle (above 50%).

Startup

The CS5421 features a programmable Soft Start function,

which is implemented through the Error Amplifier and the

external Compensation Capacitor. This feature prevents

stress to the power components and overshoot of the output

voltage during start−up. As power is applied to the regulator,

the CS5421 Undervoltage Lockout circuit (UVL) monitors

the IC’s supply voltage (VCC). The UVL circuit prevents the

MOSFET gates from switching until VCC exceeds the 8.6 V

threshold. A hysteresis function of 800 mV improves noise

immunity. The Compensation Capacitor connected to the

COMP pin is charged by a 30 μA current source. When the

capacitor voltage exceeds the 0.4 V offset of the PWM

comparator, the PWM control loop will allow switching to

occur. The upper gate driver GATE(H) is activated turning

on the upper MOSFET. The current then ramps up through

the main inductor and linearly powers the output capacitors

and load. When the regulator output voltage exceeds the

COMP pin voltage minus the 0.4 V PWM comparator offset

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