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CS5421

Dual Out−of−Phase Synchronous Buck Controller with Remote Sense

ON Semiconductor 

CS5421

ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; ROSC = 30.9 k, CCOMP1,2 = 0.1 μF,

10.8 V < VCC < 13.2 V; CGATE(H)1,2 = CGATE(L)1,2 = 1.0 nF, unless otherwise specified.)

Characteristic

Test Conditions

Min

Typ

Max

Unit

PWM Comparator

Transient Response

PWM Comparator Offset

COMP1,2 = 1.0 V, VFB1(2) = VFFB1(2) = 0 to 1.2 V

−

150

300

ns

VFFB1(2) = 0 V; Increase COMP1,2 until

GATE(H)1,2 starts switching

0.30

0.45

0.60

V

Artificial Ramp

VFFB1(2) Bias Current

VFFB1(2) Input Range

Minimum Pulse Width

Duty cycle = 50%, Note 3

VFFB1(2) = 0 V

−

−

40

70

100

mV

−

0.4

1.5

μA

0.0

−

1.1

V

−

−

300

ns

Oscillator

Switching Frequency

Switching Frequency

Switching Frequency

ROSC Voltage

Phase Difference

ROSC = 61.9 k; Measure GATE(H)2, Note 3

ROSC = 30.9 k; Measure GATE(H)2

ROSC = 11.8 k; Measure GATE(H)2, Note 3

ROSC = 30.9 k, Note 3

−

112

150

188

kHz

224

300

376

kHz

600

750

900

kHz

0.970

1.000

1.030

V

−

180

−

°

Supply Currents

VCC Current

SGND Current

COMP1,2 = 0 V (No Switching)

−

−

16

22

mA

75

150

225

μA

Undervoltage Lockout

Start Threshold

GATE(H) Switching; COMP1,2 charging

7.8

8.6

9.6

V

Stop Threshold

GATE(H) not switching; COMP1,2 discharging

7.0

7.8

8.6

V

Hysteresis

Start−Stop

0.5

0.8

1.5

V

3. Guaranteed by design, not 100% tested in production.

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

16 Lead SO Narrow

1

2

3

4

5

6

7

8

PIN SYMBOL

GATE(H)1

GATE(L)1

PGND1

LGND

SGND

VFFB1

VFB1

COMP1

9

COMP2

FUNCTION

High Side Switch FET driver pin for the channel 1 FET.

Low Side Synchronous FET driver pin for the channel 1 FET.

High Current ground for the GATE(H)1 and GATE(L)1 pins.

Logic ground. All control circuits are referenced to this pin. IC

substrate connection.

Ground sense for the internal reference.

Input for the channel 1 PWM comparator.

Error amplifier inverting input for channel 1.

Channel 1 Error Amp output. PWM Comparator reference

input. A capacitor to LGND provides Error Amp compensa-

tion. The same capacitor provides Soft Start timing for chan-

nel 1. This pin also disables the channel 1 output when

pulled below 0.3 V.

Channel 2 Error Amp output. PWM Comparator reference

input. A capacitor to LGND provides Error Amp compensa-

tion and Soft Start timing for channel 2. Channel 2 output is

disabled when this pin is pulled below 0.3 V.

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