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CS5421

Dual Out−of−Phase Synchronous Buck Controller with Remote Sense

ON Semiconductor 

CS5421

DVESR + DIOUT ESRMAX

Similarly, the maximum allowable ESL is calculated from

the following formula:

ESLMAX

+

DVESL

DI

Dt

Selection of the Input Inductor

A common requirement is that the buck controller must

not disturb the input voltage. One method of achieving this

is by using an input inductor and a bypass capacitor. The

input inductor isolates the supply from the noise generated

in the switching portion of the buck regulator and also limits

the inrush current into the input capacitors upon power up.

The inductor’s limiting effect on the input current slew rate

becomes increasingly beneficial during load transients. The

worst case is when the load changes from no load to full load

(load step), a condition under which the highest voltage

change across the input capacitors is also seen by the input

inductor. The inductor successfully blocks the ripple current

while placing the transient current requirements on the input

bypass capacitor bank, which has to initially support the

sudden load change.

The minimum inductance value for the input inductor is

therefore:

LIN

+

DV

(dIńdt)MAX

where:

LIN = input inductor value;

ΔV = voltage seen by the input inductor during a full load

swing;

(dI/dt)MAX = maximum allowable input current slew rate.

The designer must select the LC filter pole frequency so

that at least 40 dB attenuation is obtained at the regulator

switching frequency. The LC filter is a double−pole network

with a slope of −2, a roll−off rate of −40 dB/dec, and a corner

frequency:

fC

+

2p

1.0

ǸLC

where:

L = input inductor;

C = input capacitor(s).

SELECTION OF THE POWER FET

FET Basics

The use of the MOSFET as a power switch is propelled by

two reasons: 1) Its very high input impedance; and 2) Its very

fast switching times. The electrical characteristics of a

MOSFET are considered to be those of a perfect switch.

Control and drive circuitry power is therefore reduced.

Because the input impedance is so high, it is voltage driven.

The input of the MOSFET acts as if it were a small capacitor,

which the driving circuit must charge at turn on. The lower

the drive impedance, the higher the rate of rise of VGS, and

the faster the turn−on time. Power dissipation in the

switching MOSFET consists of 1) conduction losses, 2)

leakage losses, 3) turn−on switching losses, 4) turn−off

switching losses, and 5) gate−transitions losses. The latter

three losses are proportional to frequency.

The most important aspect of FET performance is the

Static Drain−To−Source On−Resistance (RDS(ON)), which

effects regulator efficiency and FET thermal management

requirements. The On−Resistance determines the amount of

current a FET can handle without excessive power

dissipation that may cause overheating and potentially

catastrophic failure. As the drain current rises, especially

above the continuous rating, the On−Resistance also

increases. Its positive temperature coefficient is between

+0.6%/°C and +0.85%/°C. The higher the On−Resistance

the larger the conduction loss is. Additionally, the FET gate

charge should be low in order to minimize switching losses

and reduce power dissipation.

Both logic level and standard FETs can be used.

Voltage applied to the FET gates depends on the

application circuit used. Both upper and lower gate driver

outputs are specified to drive to within 1.5 V of ground when

in the low state and to within 2.0 V of their respective bias

supplies when in the high state. In practice, the FET gates

will be driven rail−to−rail due to overshoot caused by the

capacitive load they present to the controller IC.

Selection of the Switching (Upper) FET

The designer must ensure that the total power dissipation

in the FET switch does not cause the power component’s

junction temperature to exceed 150°C.

The maximum RMS current through the switch can be

determined by the following formula:

ǸƪIL(PEAK)2 ) (IL(PEAK)

) IL(VALLEY)2 D

ƫ IL(VALLEY))

IRMS(H) +

3.0

where:

IRMS(H) = maximum switching MOSFET RMS current;

IL(PEAK) = inductor peak current;

IL(VALLEY) = inductor valley current;

D = duty cycle.

Once the RMS current through the switch is known, the

switching MOSFET conduction losses can be calculated:

PRMS(H) + IRMS(H)2 RDS(ON)

where:

PRMS(H) = switching MOSFET conduction losses;

IRMS(H) = maximum switching MOSFET RMS current;

RDS(ON) = FET drain−to−source on−resistance

The upper MOSFET switching losses are caused during

MOSFET switch−on and switch−off and can be determined

by using the following formula:

PSWH + PSWH(ON) ) PSWH(OFF)

+ VIN

IOUT (tRISE ) tFALL)

6.0T

where:

PSWH(ON) = upper MOSFET switch−on losses;

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