1203P60 데이터 시트보기 (PDF) - ON Semiconductor

부품명

상세내역

일치하는 목록

1203P60

NCP1203D60R2G -> 1203P60 / SOIC−8 or PDIP−8 package

ON Semiconductor 

NCP1203

12.8 V

7.8 V

VCC

4.9 V

DRIVING PULSES

Figure 15. Typical Waveforms in Short Circuit Conditions

Calculating the VCC Capacitor

The VCC capacitor can be calculated knowing the IC

consumption as soon as VCC reaches 12.8 V. Suppose that a

NCP1203P60 is used and drives a MOSFET with a 30 nC

total gate charge (Qg). The total average current is thus made

of ICC1 (700 mA) plus the driver current, Fsw x Qg or

1.8 mA. The total current is therefore 2.5 mA. The DV

available to fully startup the circuit (e.g. never reach the

7.8 V UVLO during power on) is 12.8–7.8 = 5 V. We have

a capacitor who then needs to supply the NCP1203 with

2.5 mA during a given time until the auxiliary supply takes

over. Suppose that this time was measured at around 15 ms.

CVCC

is

calculated

using

the

equation

Dt · i

C + DV

or

C w 7.5 mF. Select a 22 mF/16 V and this will fit.

Skipping Cycle Mode

The NCP1203 automatically skips switching cycles when

the output power demand drops below a given level. This is

accomplished by monitoring the FB pin. In normal

operation, pin 2 imposes a peak current accordingly to the

load value. If the load demand decreases, the internal loop

asks for less peak current. When this setpoint reaches a

determined level (Vpin 1), the IC prevents the current from

decreasing further down and starts to blank the output

pulses: the IC enters the so−called skip cycle mode, also

named controlled burst operation. The power transfer now

depends upon the width of the pulse bunches (Figure 17).

Suppose we have the following component values:

Lp, primary inductance = 350 mH

Fsw , switching frequency = 61 kHz

Ip skip = 600 mA (or 333 mV/Rsense)

The theoretical power transfer is therefore:

1

2

· Lp · Ip2 ·

Fsw

+ 3.8

W

If this IC enters skip cycle mode with a bunch length of

10 ms over a recurrent period of 100 ms, then the total power

transfer is: 3.8 . 0.1 + 380 mW.

To better understand how this skip cycle mode takes place,

a look at the operation mode versus the FB level

immediately gives the necessary insight:

FB

NORMAL CURRENT

MODE OPERATION

4.2 V, FB Pin Open

3.2 V, Upper

Dynamic Range

1V

SKIP CYCLE OPERATION

IP(min) = 333 mV/RSENSE

Figure 16.

When FB is above the skip cycle threshold (1.0 V by

default), the peak current cannot exceed 1.0 V/Rsense.

When the IC enters the skip cycle mode, the peak current

cannot go below Vpin1/3.3/Rsense. The user still has the

flexibility to alter this 1.0 V by either shunting pin 1 to

ground through a resistor or raising it through a resistor up

to the desired level. Grounding pin 1 permanently

invalidates the skip cycle operation. However, given the

extremely low standby power the controller can reach, the

PWM in no−load conditions can quickly enter the minimum

ton and still transfer too much power. An instability can take

place. We recommend in that case to leave a little bit of skip

level to always allow 0% duty cycle.

www.onsemi.com

9

Share Link: