1203P60 데이터 시트보기 (PDF) - ON Semiconductor

부품명

상세내역

일치하는 목록

1203P60

NCP1203D60R2G -> 1203P60 / SOIC−8 or PDIP−8 package

ON Semiconductor 

NCP1203

ON/OFF

1

8

2

7

3

6

Q1

4

5

Figure 19. Another Way of Shutting Down the IC without a Definitive Latch−Off State

Full Latching Shutdown

Other applications require a full latching shutdown, e.g.

when an abnormal situation is detected (overtemperature or

overvoltage). This feature can easily be implemented

through two external transistors wired as a discrete SCR.

When the VCC level exceeds the zener breakdown voltage,

the NPN biases the PNP and fires the equivalent SCR,

permanently bringing down the FB pin. The switching

pulses are disabled until the user unplugs the power supply.

OVP

Rhold

12 k

10 k

0.1 mF

10 k

NCP1203

1

8

2

7

3

6

4

5

CVCC LAux

Figure 20. Two Bipolars Ensure a Total Latch−Off of the SMPS in Presence of an OVP

Rhold ensures that the SCR stays on when fired. The bias

current flowing through Rhold should be small enough to let

the VCC ramp up (12.8 V) and down (4.9 V) when the SCR

is fired. The NPN base can also receive a signal from a

temperature sensor. Typical bipolars can be MMBT2222

and MMBT2907 for the discrete latch. The MMBT3946

features two bipolars NPN+PNP in the same package and

could also be used.

Protecting the Controller Against Negative Spikes

As with any controller built upon a CMOS technology, it

is the designer’s duty to avoid the presence of negative

spikes on sensitive pins. Negative signals have the bad habit

to forward bias the controller substrate and induce erratic

behaviors. Sometimes, the injection can be so strong that

internal parasitic SCRs are triggered, engendering

irremediable damages to the IC if they are a low impedance

path is offered between VCC and GND. If the current sense

pin is often the seat of such spurious signals, the

high−voltage pin can also be the source of problems in

certain circumstances. During the turn−off sequence, e.g.

when the user un−plugs the power supply, the controller is

still fed by its VCC capacitor and keeps activating the

MOSFET ON and OFF with a peak current limited by

Rsense. Unfortunately, if the quality coefficient Q of the

resonating network formed by Lp and Cbulk is low (e.g. the

MOSFET Rdson + Rsense are small), conditions are met to

make the circuit resonate and thus negatively bias the

controller. Since we are talking about ms pulses, the amount

of injected charge (Q = I x t) immediately latches the

controller which brutally discharges its VCC capacitor. If this

VCC capacitor is of sufficient value, its stored energy

damages the controller. Figure 21 depicts a typical negative

shot occurring on the HV pin where the brutal VCC discharge

testifies for latchup.

www.onsemi.com

11

Share Link: