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PCA9557

8-bit I2C-bus and SMBus I/O port with reset

NXP Semiconductors. 

NXP Semiconductors

PCA9557

8-bit I2C-bus and SMBus I/O port with reset

12. Dynamic characteristics

Table 11. Dynamic characteristics

Symbol Parameter

Conditions

Standard-mode

I2C-bus

Min

Max

fSCL

SCL clock frequency

tBUF

bus free time between a STOP and

START condition

0

100

4.7

-

tHD;STA

tSU;STA

hold time (repeated) START condition

set-up time for a repeated START

condition

4.0

-

4.7

-

tSU;STO

tHD;DAT

tVD;ACK

tVD;DAT

tSU;DAT

tLOW

tHIGH

tf

tr

tSP

set-up time for STOP condition

data hold time

data valid acknowledge time

data valid time

data set-up time

LOW period of the SCL clock

HIGH period of the SCL clock

fall time of both SDA and SCL signals

rise time of both SDA and SCL signals

pulse width of spikes that must be

suppressed by the input filter

4.0

0

[1]

-

[2]

-

250

4.7

4.0

-

-

-

-

-

1

1

-

-

-

300

1000

50

Port timing

tv(Q)

data output valid time

pin IO0

pins IO1 to IO7

-

250

-

200

tsu(D)

data input set-up time

th(D)

data input hold time

Reset timing

0

-

200

-

tw(rst)

trec(rst)

trst

reset pulse width

reset recovery time

reset time

6

-

0

-

400

-

Fast-mode I2C-bus

Min

Max

0

400

1.3

-

0.6

-

0.6

-

0.6

-

0

-

-

0.9

-

0.9

100

-

1.3

-

0.6

-

20 + 0.1Cb[3] 300

20 + 0.1Cb[3] 300

-

50

-

250

-

200

0

-

200

-

6

-

0

-

400

-

Unit

kHz

µs

µs

µs

µs

ns

µs

ms

ns

µs

µs

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

[1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW.

[2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.

[3] Cb = total capacitance of one bus line in pF.

PCA9557

Product data sheet

Rev. 06 — 11 June 2008

© NXP B.V. 2008. All rights reserved.

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