PCA9557 데이터 시트보기 (PDF) - NXP Semiconductors.

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PCA9557

8-bit I2C-bus and SMBus I/O port with reset

NXP Semiconductors. 

NXP Semiconductors

PCA9557

8-bit I2C-bus and SMBus I/O port with reset

slave address

SDA S 0 0 1 1 A2 A1 A0 0 A

command byte

A (cont.)

START condition

R/W

acknowledge

from slave

slave address

(cont.) S 0 0 1 1 A2 A1 A0 1 A

acknowledge

from slave

data from register

DATA (first byte)

A

data from register

DATA (last byte)

NA P

(repeated)

START condition

R/W

acknowledge

from slave

Fig 16. Read from register

acknowledge

from master

no acknowledge STOP

from master condition

at this moment master-transmitter becomes master-receiver

and slave-receiver becomes slave-transmitter

002aad283

slave address

data from port

data from port

no acknowledge

from master

SDA S 0 0 1 1 A2 A1 A0 1 A

DATA 1

A

DATA 4

NA P

START condition

R/W acknowledge

from slave

acknowledge

from master

STOP

condition

read from

port

data into

port

DATA 1

th(D)

DATA 2 DATA 3

tsu(D)

DATA 4

002aad284

Remark: This figure assumes the command byte has previously been programmed with 00h.

Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge

phase is valid (output mode). Input data is lost.

Fig 17. Read input port register

PCA9557

Product data sheet

Rev. 06 — 11 June 2008

© NXP B.V. 2008. All rights reserved.

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