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PCA9557

8-bit I2C-bus and SMBus I/O port with reset

NXP Semiconductors. 

NXP Semiconductors

PCA9557

8-bit I2C-bus and SMBus I/O port with reset

data output

by transmitter

data output

by receiver

SCL from master

1

2

S

START

condition

Fig 13. Acknowledgement on the I2C-bus

not acknowledge

acknowledge

8

9

clock pulse for

acknowledgement

002aaa987

8.4 Bus transactions

Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figure 14

and Figure 15). Data is read from the PCA9557 registers using Read and Receive Byte

transfers (see Figure 16 and Figure 17).

SCL 1 2 3 4 5 6 7 8 9

slave address

command byte

SDA S 0 0 1 1 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A

data to port

DATA 1

STOP

condition

AP

START condition

write to port

data out from port

R/W acknowledge

from slave

Fig 14. Write to output port register

acknowledge

from slave

acknowledge

from slave

tv(Q)

DATA 1 VALID

002aad281

SCL 1 2 3 4 5 6 7 8 9

slave address

command byte

SDA S 0 0 1 1 A2 A1 A0 0 A 0 0 0 0 0 0 1 1/0 A

data to register

DATA

START condition

R/W acknowledge

from slave

acknowledge

from slave

Fig 15. Write to I/O configuration or polarity inversion registers

STOP

condition

AP

acknowledge

from slave

002aad282

PCA9557

Product data sheet

Rev. 06 — 11 June 2008

© NXP B.V. 2008. All rights reserved.

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