FX805 데이터 시트보기 (PDF) - CML Microsystems Plc
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FX805 Datasheet PDF : 17 Pages
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Controlling Protocol
Control of the FX805 Sub-Audio Signalling Processor's operation is by communication between the µController and the
FX805 internal registers on the “C-BUS,” using Address/Commands (A/Cs) and appended instructions or data (see Figure 9).
The use and content of these instructions is detailed in the following paragraphs and tables. The Address Select input enables
the addressing of 2 separate FX805s on the “C-BUS” to provide full-duplex multi-mode signalling.
FX805 Internal Registers
FX805 internal registers are detailed below:
Control Register (70H/78H) – Write only, control and
configuration of the FX805.
Status Register (71 /79 ) – Read Only, reporting of device
HH
functions.
CTCSS Rx Frequency Register (72 /7A ) – Read Only,
H
H
a 2-byte binary word indicating the frequency of the
received sub-audio input.
CTCSS Tx Frequency / NRZ Tx or Rx Baud Rate Register
(73H/7BH) – Write Only, a 2-byte command to set the
relevant parameters.
NRZ Rx Data Register (74H/7CH) – Read Only, a single-byte
of received NRZ data.
NRZ Tx Data Register (75 /7D ) – Write Only, to load a
H
H
single-byte of NRZ data for transmission one byte at a
time.
Gain-Set Register (76 /7E ) – Write Only, a single byte to
H
H
set the gain of the Tx Lowpass Filter.
Address/Commands
The first byte of a loaded data sequence is always
recognized by the “C-BUS” as an Address/Command (A/C)
byte. Instruction and data transactions to and from this
device consist of an Address/Command byte followed by
either:
(i) further instructions or data or,
(ii) a Status or data Reply.
Instructions and data are loaded and transferred, via
“C-BUS,” in accordance with the timing information given in
Figures 9 and 10.
Placing the Address Select input at a logic “0” will address
FX805 No.1, a logic “1” will address FX805 No.2.
Tables 1 and 2 show the list of A/C bytes relevant to the
FX805. A complete list of DBS 800 “C-BUS” Address
allocations is published in the System Support Document.
Command
Assignment
Address/Command (A/C) Byte +
Hex.
Binary
MSB
LSB
General Reset
01
Write to Control Reg.
70
Read Status Reg.
71
Read CTCSS Rx Freq. Reg.
72
Write to CTCSS Tx Frequency/ 73
NRZ Baud Rate Reg.
Read NRZ Rx Data Reg.
74
Write to NRZ Tx Data Reg.
75
Write to Gain-Set Reg.
76
00000001
01110000 +
01110001 +
01110010 +
01110011 +
01110100 +
01110101 +
01110110 +
Table 1 – FX805 No.1 “C-BUS” Address/Commands
Data
Byte/s
1 byte Instruction to Control Reg.
1 byte Reply from Status Reg.
2 byte Reply of CTCSS Rx data
2 byte Instruction for Tx Frequency
and NRZ Tx/Rx baud rates
1 byte binary data Reply
1 byte binary data Command
1 byte Instruction for Tx Output
Address Select input at a logic “0”
Command
Assignment
Address/Command (A/C) Byte +
Hex.
Binary
MSB
LSB
General Reset
01
Write to Control Reg.
78
Read Status Reg.
79
Read CTCSS Rx Frequency Reg. 7A
Write to CTCSS Tx Frequency/ 7B
NRZ Baud Rate Reg.
Read NRZ Rx Data Reg.
7C
Write to NRZ Tx Data Reg.
7D
Write to Gain-Set Reg.
7E
00000001
01111000 +
01111001 +
01111010 +
01111011 +
01111100 +
01111101 +
01111110 +
Table 2 – FX805 No.2 “C-BUS” Address/Commands
6
Data
Byte/s
1 byte Instruction to Control Reg.
1 byte Reply from Status Reg.
2 byte Reply of CTCSS Rx data
2 byte Instruction for Tx Frequency
and NRZ Tx/Rx baud rates
1 byte binary data Reply
1 byte binary data Command
1 byte Instruction for Tx Output
Address Select input at a logic “1”
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