M37640E8 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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M37640E8

Single-Chip 8-BIT CMOS Microcontroller M37640E8-XXXFP Specification

MITSUBISHI ELECTRIC  

7600 Series

M37640E8-XXXF Preliminary Specification

Mitsubishi Microcomputers

2.6.2 Peripheral Interface and Access Timing

The M37640 offers a wide variety of peripherals. These include RAM, EPROM, UARTs, SIOs, 8-bit

and 16-bit timers, various I/O ports, clock generators, and USB core.

The interface between the CPU, the peripheral decode block, and peripheral blocks is shown in

Figure 2-24. Signals DB7 to DB0, AB2 to AB0, R/W, EB, and at least one peripheral decode (PDnB)

are routed to each peripheral. The address signals and peripheral decode signal are used in the

peripheral block to create decode signals for each register. Because three address bits are available at

the peripheral, a maximum of eight decode signals can be created for each peripheral decode signal.

If the peripheral contains more than eight registers, additional peripheral decode signals are routed to

the peripheral.

[P1]

CPU P2

DB[7:0]

RDbuf

perDB[7:0]

[P2]

P1

PD1

R/W

E

P2

AB[2:0], R/W, EB

AB[15:0]

Peripheral PD1B

Decode

PD2B

.

.

.

.

.

.

.

PDNB

Reg

D1

P1

decode D2

.. AB

PD1 DN

P1

Figure 2-24. Internal Peripheral Interface

P2

R/W WRreg

E

D1

D1

E

RDreg

R/W

Register 1

Register 2

Register N

Peripheral 1

Peripheral 2

Peripheral N

2-26

7/9/98

Peripheral Interface

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