M37640E8 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC
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M37640E8 Datasheet PDF : 172 Pages
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Mitsubishi Microcomputer
7600 Series
M37640E8-XXXF Preliminary Specification
2.6 Peripheral Interface
2.6.1 Chip Bus Timing
The internal bus timing is described below for the CPU (or DMAC) writing to and reading from a
peripheral (see Figure 2-23.)
• The address (AB[15:0]) is output from the CPU on P2.
• The data bus (DB[7:0]) is driven by the CPU during a write, or by a peripheral during a read,
on P1.
• The R/W signal is high for a read and low for a write, and changes on P2.
• The EB signal is high when a read or write is not valid, and is low for a valid read or write. It
changes on P2.
• A PDnB signal (peripheral decode) is assigned to each peripheral and is low when reading from
or writing to the peripheral. Each PDnB signal is clocked on P2 timing.
The address, R/W, EB, and PDnB signals are latched at the peripheral block on P1, so they must all
be valid before this time. The data bus is latched by the CPU during a read, or by a peripheral during
a write, on P2; so the value on the data bus must be valid before this time.
2*Φ
P1
P2
AB[15:0], R/W, EB,
PDnB [P2]
AB[15:0], R/W, EB,
PDnB latched @
peripheral [P1]
AB[2:0], R/W, EB,
PDnB peripheral [P1]
DB[7:0] [P1]
DB[7:0] latched [P2]
Figure 2-23. M37640 Internal Bus Timing
Peripheral Interface
7/9/98
2-25
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