MK50H27(1997) 데이터 시트보기 (PDF) - STMicroelectronics

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MK50H27
(Rev.:1997)

Signalling System 7 Link Controller

STMicroelectronics 

MK50H27

04:03

BURST

02

BSWPD

01

ACON

00 BCON

”Non-data DMA transfers refers to any DMA transfers that access

memory other than the data buffers themselves. This includes the

Initialization Block, Descriptors, and Status Buffer. It has no effect

on data DMA transfers. BSWPC allows the MK50H27 to operate with

memory organizations that have bits 07:00 at even addresses and

with bits 15:08 at odd addressses or vice versa. BSWPC is

Read/Write and cleared by BUS RESET.

With BSWPC = 1:

Address

Address

XX1 0 . . . 7

XX1 8 . . . 15

This memory organization is used with the 8086 family of microproces-

sors.

With BSWPC = 0:

Address

Address

XX0 8 . . . 15

XX1 0 . . . 7

This memory organization is used with the 68000 and the Z8000

microprocessors.

This field determines the maximum number of data transfers

performed each time control of the host bus is obtained. BURST

is READ/WRITE and cleared on bus Reset.

BURST <1:0>

8 bit mode

16 bit mode

00

2 bytes

1 words

10*

16 bytes

8 words

01

unlimited

unlimited

* Suggested setting

This bit determines the byte ordering of all data DMA transfers.

Data transfers are those to or from a data buffer. BSWPD has no ef-

fect on non-data transfers. The effect of BSWPD on data transfers is

the same as that of BSWPC on non-data transfers (see

above). For most applications, including most 68000 based sys-

tems, this bit should be set.

ALE CONTROL defines the assertive state of pin 18 when the

MK50H27 is a Bus Master. ACON is READ/ WRITE and cleared by

Bus RESET.

ACON

0

1

PIN18

ASSERTED HIGH

ASSERTED LOW

NAME

ALE

AS

BYTE CONTROL redefines the Byte Mask and Hold I/O pins.

BCON is READ/WRITE and cleared by Bus RESET.

BCON

0

1

PIN16

BM1

BUSAKO

PIN15

BM0

BYTE

PIN17

HOLD

BUSRQ

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