MT9042 데이터 시트보기 (PDF) - Mitel Networks
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MT9042 Datasheet PDF : 16 Pages
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Preliminary Information
MT9042
maximum time interval error should not exceed 1µs.
As well, during this transient response, the output
signal shall not change its phase position in time
faster than 81 ns per 1.326 ms observation period.
For the case where the PRI and SEC reference
inputs are both at 8 kHz, but phase separated by
180° the maximum time interval recorded for input
rearrangement is 320 ns. For a 45 degree separation
of the reference inputs, an 85 Hz periodic
rearrangement indicated a measured slope of 10ns
per 1.326 ms observation period.
Jitter Performance
The output jitter of a digital trunk PLL is composed of
intrinsic jitter, measured using a jitter free reference
clock, and frequency dependent jitter, measured by
applying known levels of jitter on the references
clock. The jitter spectrum indicates the frequency
content of the output jitter.
Intrinsic Jitter
Intrinsic jitter is the jitter added to an output signal by
the processing device, in this case the enhanced
PLL. Tables 6 and 7 show the average measured
intrinsic jitter of the T1 and E1 outputs. Each
measurement is an average based upon a ±100 ppm
deviation (in steps of 20 ppm) on the input reference
clock. Jitter on the master clock will increase intrinsic
jitter of the device, hence attention to minimization of
master clock jitter is required.
Jitter Transfer Function
The jitter transfer function is a measure of the
transfer characteristics of the PLL to frequency
specific jitter on the referenced input of the PLL. It is
directly linked to the loop bandwidth and the
magnitude of the phase error suppression
characteristics of the PLL. It is measured by applying
jitter of specific magnitude and frequencies to the
input of the PLL, then measuring the magnitude of
the output jitter (both filtered and unfiltered) on the
T1 or E1 output.
Care must be taken when measuring the transfer
characteristics to ensure that critical jitter alias
frequencies are included in the measurement (i.e.,
for digital phase locked loops using an 8 kHz input).
Tables 8 and 9 provide measured results for the jitter
transfer characteristics of the PLL for both a 1.544
MHz and 2.048 MHz reference input clock. The
transfer characteristics for an 8 kHz reference input
will be the same.
Figures 5 and 6 show the jitter attenuation
performance of the T1 and E1 outputs plotted
against AT & T TR62411 and ETSI requirements,
respectively.
Output Jitter in UIp-p
Reference Input
FLT0 Unfiltered
FLT1
10Hz - 8kHz
FLT2
10Hz - 40kHz
FLT3
8kHz - 40kHz
8 kHz
.011
.004
.006
.002
1.544 MHz
.011
.001
.002
.001
2.048 MHz
.011
.001
.002
.001
Table 6 -Typical Intrinsic Jitter for the T1 Output
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Output Jitter in UIp-p
Reference Input
FLT0 Unfiltered
FLT1
20Hz - 100kHz
FLT2
700Hz - 100kHz
8 kHz
.011
.002
.002
1.544 MHz
.011
.002
.002
2.048 MHz
.011
.002
.002
Table 7 - Typical Intrinsic Jitter for the E1 Output
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-103
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