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MT9042

Global Digital Trunk Synchronizer

Mitel Networks 

MT9042

Preliminary Information

Functional Description

Modes of Operation

The MT9042 is a fully digital, phase-locked loop

designed to provide timing references to interface

circuits for T1 and E1 Primary Rate Digital

Transmission links. As shown in Figure 1, the PLL

consists of an input reference selection circuit (MUX),

a Time Interval Error corrector (TIE), and a PLL that

employs a high resolution Digitally Controlled

Oscillator (DCO) to generate the T1 and E1 outputs.

The MT9042 accepts two reference clock inputs,

primary (PRI) and secondary (SEC) both connected

to independent external reference sources, either of

which can be selected as reference for

synchronization by the reference select (RSEL)

input. The selected reference signal is then

regenerated by the TIE correction circuit and passed

as a virtual reference to the PLL. The TIE correction

circuit will limit phase jumps (as specified by AT & T

TR62411 and ETSI ETS 300 011) during

rearrangement between the external reference

clocks. This virtual reference is then used by the

PLL for synchronizing the output signals.

The interface circuit on the output of the DCO

generates 1.544 MHz (C1.5), 3.088 MHz (C3), 2.048

MHz (C2), 4.096 MHz (C4), 8.192 MHz (C8), 16.384

MHz (C16), and three 8 kHz frame pulses F0o, FP8-

STB, and FP8-GCI.

Phase

fref Detector

Loop

Filter

DCO

fsync

Divider

Figure 3 - PLL Block Diagram

As shown in Figure 3, the PLL of the MT9042

consists of a phase detector (PD), a loop filter, a high

resolution DCO, and a digital frequency divider. The

digitally controlled oscillator (DCO) is locked in

frequency (n x fref) to one of three possible reference

frequencies, configured using pins FSEL1 and

FSEL2. Combined with the reference select input

RSEL, the PLL is capable of providing a full range of

E1/T1 clock signals synchronized to either the

primary PRI or secondary SEC input. The loop filter

is a first order lowpass structure that provides

approximately a 2 Hz bandwidth.

The MT9042 can operate in one of two modes,

MANUAL or AUTOMATIC, as controlled by mode

select pins MS1 and MS2 (see Table 1). In MANUAL

mode, the user is responsible for switching

references during NORMAL operation, as well as

forcing the PLL into FREERUN or HOLDOVER

states.

When AUTOMATIC mode is selected, operation is

controlled by an internal state machine. Under state

machine control, input reference selection is

automatically based upon the input levels of LOSS1

and LOSS2.

MS2 MS1 Description of Operation

0

0 NORMAL (manual mode)

0

1 HOLDOVER (manual mode)

1

0 FREERUN (manual mode)

1

1 AUTOMATIC MODE

Table 3- Operating Modes of the MT9042

Manual Mode

In MANUAL mode operation, the input reference

selection is accomplished through a 2-to-1

multiplexer, which is controlled by the RSEL input

pin. As shown in Table 2, for MANUAL mode

operation RSEL=0 selects PRI as the primary

reference input, while RSEL=1 selects SEC as the

primary reference input.

Mode

RSEL

Reference Input

Selected

Manual

Manual

0 PRI

1 SEC

Automatic

Automatic

0 state machine control

1 state machine control, but

treats SEC as primary

and PRI as secondary

Table 4- Reference Input Selection of the MT9042

There are three possible input frequencies for

selection as the primary reference clock. These are 8

kHz, 1.544 MHz or 2.048 MHz. Frequency selection

is controlled by the logic levels of FSEL1 and FSEL2,

as shown in Table 3. This variety of input frequencies

was chosen to allow the generation of all the

necessary T1 and E1 clocks from either a T1, E1 or

frame pulse reference source.

3-100

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