CDP1877 데이터 시트보기 (PDF) - Intersil

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CDP1877

Programmable Interrupt Controller (PIC)

Intersil 

CDP1877, CDP1877C

The Low Order Vector Address will be set according to the table below:

LOW ADDRESS BITS

INTERVAL SELECTED NO. OF BYTES

BIT B7

BIT B6

BIT B5

2

SETS A7

SETS A6

SETS A5

4

SETS A7

SETS A6

SETS A5

8

SETS A7

SETS A6

X

16

SETS A7

X

X

NOTES:

1. X = Don’t Care

2. All Don’t Care addresses and addresses A0-A3 are determined by interrupt request.

Mask Register

A ”1” written into any location in this write only register will

mask the corresponding interrupt request line. All interrupt

inputs (except CASCADE) are maskable.

BUS 7

M7

M6

MASK REGISTER BITS

M5

M4

M3

M2

Status Register

In this read only register a “1” will be present in the

corresponding bit location for every masked or unmasked

pending interrupt.

BUS 0

M1

M0

BUS 7

S7

S6

STATUS REGISTER BITS

S5

S4

S3

S2

Polling Register

This read only register provides the low order vector address

and is used to identify the source of interrupt if a polling

technique, rather than interrupt servicing, is used.

BUS 0

S1

S0

BUS 7

P7

P6

POLLING REGISTER BITS

P5

P4

P3

P2

BUS 0

P1

P0

BIT B4

SET A4

X

X

X

WRITE ONLY

READ ONLY

READ ONLY

RESPONSE TO INTERRUPT (AFTER S3 CYCLE)

The PIC’s response to interrogation by the CPU is always 3

bytes long, placed on the data bus in consecutive bytes in

the following format:

First (Instruction) Byte:

LONG BRANCH INSTRUCTION - CO (Hex)

BUS 7

BUS 0

1

1

0

0

0

0

0

0

4-86

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