IDT70V08S/L
High-Speed 64K x 8 Dual-Port Static RAM
Waveform of Read Cycles(5)
tRC
ADDR
CE(6)
(4)
tAA
tACE(4)
tAOE(4)
OE
Industrial and Commercial Temperature Ranges
R/W
DATAOUT
tLZ (1)
tOH
VALID DATA(4)
BUSYOUT
tBDD(3,4)
tHZ(2)
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NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
Timing of Power-Up Power-Down
CE
tPU
ICC
50%
ISB
tPD
50%
,
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8