IDT70V08S 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT70V08S

HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT70V08S/L

High-Speed 64K x 8 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

tSAA

A0-A2

VALID ADDRESS

VALID ADDRESS

SEM

I/O

R/W

tAW

tWR

tEW

tDW

DATAIN VALID

tAS

tWP

tDH

tSOP

tACE

tOH

DATA OUT

VALID(2)

tSWRD

tAOE

OE

Write Cycle

Read Cycle

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).

2. DATAOUT VALID represents I/O0-7 equal to semaphore value.

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Timing Waveform of Semaphore Write Contention(1,3,4)

A0"A"-A2"A"

MATCH

SIDE(2) "A"

R/W"A"

SEM"A"

A0"B"-A2"B"

SIDE(2) "B"

R/W"B"

tSPS

MATCH

SEM"B"

NOTES:

1. DOR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.

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