Description
The device CMOS Dynamic RAM organized as 1,048,576 words x 16 bits with extended data out access mode. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V oniy power supply. Low voltage operation is more suitable to be used on battery backup, portable electronic application. A new refresh feature called “self-refresh” is supported and very slow CBR cycles are being performed. lt is packaged in JEDEC standard 42-pin plastic SOJ.

FEATUREs
• Single 5V(±10%) or 3.3V(±10%) only power supply
• High speed tRAC acess time: 50/60ns
• Low power dissipation
   - Active wode : 5V version 660/605 mW (Mas)
                            3.3V version 432/396 mW (Mas)
   - Standby mode: 5V version 1.375 mW (Mas)
                               3.3V version 0.54 mW (Mas)
• Extended - data - out(EDO) page mode access
• I/O level: TTL compatible (Vcc = 5V)
                  LVTTL compatible (Vcc = 3.3V)
• 1024 refresh cycle in 16 ms(Std.) or 128 ms(S-version)
• 4 refresh modes:
   - RAS only refresh
   - CAS - before - RAS refresh
   - Hidden refresh
   - Self-refresh(S-version)