ARCHITECTURE AND OPERATION
The UT1553B RTI is an interface device linking a MILSTD-1553 serial data bus and a host microprocessor system. The RTI’s MIL-STD-1553B interface includes encoding/decoding logic, error detection, command recognition, memory address control, clock, and reset circuits.

FEATURES
❐ Complete MIL-STD-1553B Remote Terminal interface compliance
❐ Dual-redundant data bus operation supported
❐ Internal illegalization of selected mode code commands
❐ External illegal command definition capability
❐ Automatic DMA control and address generation
❐ Operational status available via dedicated lines or internal status register
❐ ASD/ENASC (formerly SEAFAC) tested and approved
❐ Available in ceramic 84-lead leadless chip carrier and 84-pin pingrid array
❐ Full military operating temperature range, -55°C to +125°C, screened to the specific test methods listed in Table I of MIL-STD-883, Method 5004, Class B
❐ JAN-qualified devices available