INTRODUCTION
The UT54LVDS032LVT with internal 100Ω Integrated Termination Resistor Quad Receiver is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400.0 Mbps (200 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology.

FEATURES
❐ >400.0 Mbps (200 MHz) switching rates
❐ +340mV differential signaling
❐ 3.3 V power supply
❐ TTL compatible outputs
❐ Cold spare all pins
❐ Nominal 100Ω Integrated Termination Resistor
❐ 3.3ns maximum propagation delay
❐ 0.35ns maximum differential skew
❐ Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019
   - Total-dose: 300 krad(Si) and 1Mrad(Si)
   - Latchup immune (LET > 100 MeV-cm2/mg)
❐ Packaging options:
   - 16-lead flatpack (dual in-line)
❐ Standard Microcircuit Drawing 5962-04201
   - QML Q and V compliant part
❐ Compatible with IEEE 1596.3SCI LVDS
❐ Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard