SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

DESCRIPTION
The TH50VSF2582/2583AASB is a mixed multi-chip package containing a 4,194,304-bit full CMOS SRAM and a 33,554,432-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration. The power supply for the TH50VSF2582/2583AASB can range from 2.7 V to 3.6 V. The TH50VSF2582/2583AASB can perform simultaneous read/write operations on its flash memory and is available in a 69-pin BGA package, making it suitable for a variety of applications.

FEATURES
• Power supply voltage
    VCCs = 2.7 V~3.6 V
    VCCf = 2.7 V~3.6 V
• Data retention supply voltage
    VCCs = 1.5 V~3.6 V
• Current consumption
    Operating: 45 mA maximum (CMOS level)
    Standby: 7 µA maximum (SRAM CMOS level)
    Standby: 10 µA maximum (flash CMOS level)
• Block erase architecture for flash memory
    8 blocks of 8 Kbytes
    63 blocks of 64 Kbytes
• Function mode control for flash memory
    Compatible with JEDEC-standard commands
• Flash memory functions
    Simultaneous Read/Write operations
    Auto-Program
    Auto Chip Erase, Auto Block Erase
    Auto Multiple-Block Erase
    Program Suspend/Resume
    Block-Erase Suspend/Resume
    Data Polling / Toggle Bit function
    Block Protection / Boot Block Protection
    Support for automatic sleep and hidden ROM area
    Common flash memory interface (CFI)
    Byte/Word Modes
• Erase and Program cycles for flash memory
    105 cycles (typical)
• Boot block architecture for flash memory
    TH50VSF2582AASB: Top boot block
    TH50VSF2583AASB: Bottom boot block
• Package
    P-FBGA69-1209-0.80A3: 0.31 g (typ.)