DESCRIPTION
The SY100S360 is a dual parity checker/generator and is designed for use in high-performance ECL systems. The inputs are segmented into two groups of nine inputs each and the parity output is at a logic LOW when an even number of inputs are at a logic HIGH. In each group, one of the nine inputs (Ia, Ib) has a shorter propagation delay and, therefore, is ideal as the expansion input for parity generation of wider data.

FEATURES
■ Max. propagation delay of 2200ps
■ IEE min. of –70mA
■ Industry standard 100K ECL levels
■ Extended supply voltage option: VEE = –4.2V to –5.5V
■ Voltage and temperature compensation for improved noise immunity
■ Internal 75kΩ input pull-down resistors
■ 15% faster than Fairchild 300K
■ Approximately 30% lower power than Fairchild 300K
■ Function and pinout compatible with Fairchild F100K
■ Available in 28-pin PLCC package