General Description
As its predecessors SDA 525x the SDA 525x-2 contains a slicer for VPS and TTX, an accelerating acquisition hardware module, a display generator for “Level 1.5” TTX data, and an 8 bit microcontroller running at 333 ns cycle time. The controller with dedicated hardware guarantees flexibility, does most of the internal processing of TTX acquisition, transfers data to/from the external memory interface and receives/transmits data via I2C user interface. The block diagram shows the internal organization of the SDA 525x-2.
The slicer combined with dedicated hardware stores TTX data in a VBI buffer of 746 Byte. The microcontroller firmware performs all the acquisition tasks (hamming- and parity-checks, page search and evaluation of header control bits) once per field.

Complete Feature List Including New Features
New features compared to SDA 525x-Specification, version 06/96 are printed in italic and bold. As described in the errata sheet 03/97, release 1.0, the newer versions of the SDA 525x and the SDA 525x-2 will not have a serial port (UART) any more.
• Acquisition:
   – Feature selection via special function register
   – Simultaneous reception of TTX, VPS, and WSS
   – Fixed framing code for VPS and TTX
   – Acquisition during VBI
   – Direct access to VBI RAM buffer
   – Acquisition of packets x/26, x/27, 8/30 (firmware)
   – Assistance of all relevant checks (firmware)
   – 1-bit framing code error tolerance (switchable)
• Display:
   – Features selectable via special function register
   – 50/60 Hz display (optional 100 Hz)
   – Level 1.5 serial attribute display pages
   – Blanking and contrast reduction output
   – 8 direct addressable display pages for SDA 5250-2, SDA 5254-2 to SDA 5257-2 (optional 10 pages)
   – 1 direct addressable display page for SDA 5251-2 to SDA 5253-2
   – 12 × 10 character matrix
   – 96 character ROM (standard G0 character set)
   – 156 national option characters for 12 languages (for European version)
   – 288 characters for X/26 display
   – 64 block mosaic graphic characters
   – 32 characters for OSD in expanded character ROM + 32 characters inside OSD box
   – Conceal/reveal
   – Transparent foreground/background - inside/outside of a box
   – Contrast reduction inside/outside of a box
   – Cursor (color changes from foreground to background color)
   – Flash (flash rate 1s, not depending on field rate)
   – Programmable horizontal and vertical sync delay
   – Full screen background color in outer screen
   – Double size/double width/double height characters
• Synchronization:
   – Display synchronization to sandcastle or Horizontal Sync (HS) and Vertical Sync (VS)
• Microcontroller:
   – 8 bit C500-CPU (8051 compatible)
   – CPU-clock 18 MHz, external 6-MHz-crystal
   – 333 ns instruction cycle
   – Parallel 8-bit data and 16 … 19-bit address bus (ROMless-Version)
   – Eight 16-bit data pointer registers (DPTR)
   – Two 16-bit timers
   – Watchdog timer
   – Capture compare timer for infrared remote control decoding
   – 256 bytes on-chip RAM
   – 8 KByte on-chip display-RAM (access via MOVX) SDA 5250-2, SDA 5254-2 to
SDA 5257-2 (optional 10 Kbyte)
   – 1 Kbyte on-chip display-RAM (access via MOVX) for SDA 5251-2 to SDA 5253-2
   – 1 Kbyte on-chip ACQ-buffer-RAM (access via MOVX)
   - 1 Kbyte on-chip extended-RAM (access via MOVX) for SDA 5250-2 and
SDA 5254-2 to SDA 5257-2
   – 6 channel 8-bit pulse width modulation unit
   – 2 channel 14-bit pulse width modulation unit
   – 4 multiplexed ADC inputs with 8-bit resolution
   – One 8-bit I/O port with open drain output and optional I2C-Bus emulation
   – Two 8-bit multifunctional I/O ports
   – One 4-bit port working as digital or analog inputs
   – One 3-bit I/O port with optional RAM/ROM address expansion up to 512 Kbyte (ROMless-Version)
• P-SDIP-52-1/P-MQFP-64-1 package for ROM-Versions (SDA 5251-2 to SDA 5253-2, SDA 5254-2 to SDA 5257-2)
• P-MQFP-80-1 package for ROMless-Version (SDA 5250M-2)
• P-LCC-84-2 package for Emulator-Version (SDA 5250-2)
• 5 V supply voltage