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전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크
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R5F565NEEDFC 데이터시트 - Renesas Electronics

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R5F565NEEDFC

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246 Pages

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2.7 MB

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Renesas
Renesas Electronics Renesas

Renesas MCUs

   120-MHz 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 2-MB flash memory (supportive of the dual bank function), 640-KB SRAM, various communications interfaces including Ethernet MAC, SD host interface (optional), SD slave interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, Encryption functions (optional), CMOS camera interface, Graphic-LCD controller, 2D drawing engine


FEATUREs
◾ 32-bit RXv2 CPU core
   • Max. operating frequency: 120 MHz
      Capable of 240 DMIPS in operation at 120 MHz
   • Single precision 32-bit IEEE-754 floating point
   • Two types of multiply-and-accumulation unit (between memories
      and between registers)
   • 32-bit multiplier (fastest instruction execution takes one CPU clock
      cycle)
   • Divider (fastest instruction execution takes two CPU clock cycles)
   • Fast interrupt
   • CISC Harvard architecture with 5-stage pipeline
   • Variable-length instructions: Ultra-compact code
   • Supports the memory protection unit (MPU)
   • JTAG and FINE (one-line) debugging interfaces
◾ Low-power design and architecture
   • Operation from a single 2.7- to 3.6-V supply
   • Low power consumption: A product that supports all peripheral
      functions draws only 0.19 mA/MHz (Typ.).
   • RTC is capable of operation from a dedicated power supply.
   • Four low-power modes
◾ On-chip code flash memory
   • Supports versions with up to 2 Mbytes of ROM
   • No wait cycles at up to 50 MHz or when the ROM cache is hit, 
      one-wait state at up to 100 MHz, two-wait state at above 100 MHz
   • User code is programmable by on-board or off-board programming.
   • Programming/erasing as background operations (BGOs)
   • A dual-bank structure allows exchanging the start-up bank.
◾ On-chip data flash memory
   • 32 Kbytes, reprogrammable up to 100,000 times
   • Programming/erasing as background operations (BGOs)
◾ On-chip SRAM, no wait states
   • 256K/640 Kbytes of SRAM (no wait states)
   • 8 Kbytes of standby RAM (backup on deep software standby)
◾ Data transfer
   • DMACAa: 8 channels
   • DTCb: 1 channel
   • EXDMAC: 2 channels
   • DMAC for the Ethernet controller: 1 channel
(Continue ...)


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