Renesas MCUs
54 MHz 32-bit RX MCU with FPU, 90 DMIPS, up to 2-Mbyte flash memory, 12-bit ADC, 10-bit DAC, ELC, MPC, CEC transmission/reception, remote control signal reception
FEATUREs
◾ 32-bit RX CPU core
• Max. operating frequency: 54 MHz
Capable of 90 DMIPS in operation at 54 MHz
• Two types of multiply-and-accumulation unit (between
memories and between registers)
• 32-bit multiplier (fastest instruction execution takes one
CPU clock cycle)
• Divider (fastest instruction execution takes two CPU clock
cycles)
• Fast interrupt
• CISC Harvard architecture with 5-stage pipeline
• Variable-length instructions, ultra-compact code
• Supports the Memory Protection Unit (MPU)
• On-chip debugging circuit
◾ Low power design and architecture
• Operation from a single 2.7 to 3.6 V or 4.0 to 5.5 V supply
• Four low power consumption modes
◾ On-chip main flash memory, no wait states
• 54-MHz operation, 18.5-ns read cycle
• 1 to 2 Mbytes supported
• User code is programmable by on-board
◾ On-chip data flash memory
• 32 Kbytes capacities
(Number of times of reprogramming: 100,000)
• Programming/erasing as background operations (BGOs)
◾ On-chip SRAM, no wait states
• 128-Kbyte size capacities
• For instructions and operands
◾ DMA
• DMAC: Incorporates four channels
• DTC
◾ ELC
• Module operation can be initiated by event signals without
going through interrupts.
• Modules can operate while the CPU is sleeping.
◾ Reset and supply management
• Power-on reset (POR)
• Low voltage detection (LVD) with voltage settings
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