FEATURES
• Quad cell delineation device operating up to a maximum rate of 52 Mbit/s.
• Provides a UTOPIA Level 2 compatible ATM-PHY Interface.
• Implements the Physical Layer Convergence Protocol (PLCP) for DS1
   transmission systems according to the ATM Forum User Network Interface
   Specification and ANSI TA-TSY-000773, TA-TSY-000772, and
   E1transmission systems according to the ETSI 300-269 and ETSI 300-270.
• Uses the PMC-Sierra PM4341 T1XC, PM4344 TQUAD, PM6341 E1XC, and
   PM6344 EQUAD T1 and E1 framer/line interface chips for DS1 and E1
   applications.
• Provides programmable pseudo-random test pattern generation, detection,
   and analysis features.
• Provides integral transmit and receive HDLC controllers with 128-byte FIFO
   depths.
• Provides performance monitoring counters suitable for accumulation periods
   of up to 1 second.
• Provides an 8-bit microprocessor interface for configuration, control and
   status monitoring.
• Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board
   test purposes.
• Low power 3.3V CMOS technology with 5V tolerant inputs.
• Available in a high density 256-pin SBGA package (27mm x 27mm).

APPLICATIONS
• ATM Switches, Multiplexers, and Routers
• SMDS Switches, Multiplexers and Routers
• DSLAM
• Integrated Access Devices (IAD)