Product Description
PI6CVF857 PLL clock device is developed for registered DDR DIMM applications. The device is a zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]), and one differential pair feedback clock outputs (FBOUT,FBOUT) . The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V LVCMOS input (PWRDWN), and the Analog Power input (AVDD). When input PWRDWN is low while power is applied, the input receivers are disabled, the PLL is turned off, and the differential clock outputs are 3-stated. When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes.

Product Features
• Operating Frequency up to 220 MHz for PC3200 Registered
   DIMM applications
• Distributes one differential clock input pair to ten differential
   clock output pairs
• Inputs (CLK,CLK) and (FBIN,FBIN)
• Input PWRDWN: LVCMOS
• Outputs (Yx, Yx), (FBOUT, FBOUT)
• External feedback pins (FBIN,FBIN) are used to
   synchronize the outputs to the clock input
• Operates at 2.5V for PC1600, PC2100, PC2700,
   and 2.6V for PC3200
• Packaging (Pb-free & Green available, select packages):
   – 48-pin TSSOP
   – 40-pin TQFN
   – 56-ball VFBGA