Product Description
The PI6C9930 Clock Buffer offers zero-delay, low-skew system clock distribution. These multiple output clock drivers optimize the timing of high-performance computer systems. Each of eight individual drivers can drive series-terminated transmission lines with impedances as low as 50Ω while delivering minimal output skews and full-swing logic levels.

FEATUREs
• Near zero input to output delay
• Seven copies of the REF/2 or Six copies of REF plus one REF × 2
• 25 – 100 MHz output
• 50% duty cycle
• Low skew
• Low jitter (<250ps cycle-to-cycle)
• Low noise balanced drive outputs
• VCC = 3.3V –0.3V, TA = 0° to 70°
• 24-pin 209 mil wide SSOP (H)
• 24-pin 150 mil wide QSOP (Q)
• 24-pin 300 mil wide SOIC (S)

APPLICATIONs
• PCI 66 MHz or 33 MHz systems