Introduction
The MUNICH128X is a 128-channel WAN Protocol Controller which provides four independent 24/32-channel HDLC controllers, each with a dedicated 64-channel DMA Controller and a Serial PCM Interface Controller. The device is offered in a 160- pin MQFP package, making it ideal for high-port-density applications.

FEATUREs
Four independent 24/32-channel HDLC PCM Controllers with common PCI interface. Each of them provides:

• Dedicated 1024 byte Tx Buffer
• Dedicated 1024 byte Rx Buffer
• Dedicated Serial PCM Interface Controller
    – T1 rates: 1.536, 1.544, 3.088, 6.176 Mbit/s
    – E1 rates: 2.048, 4.096, 8.192 Mbit/s
• Dedicated 64-channel DMA Controller
    – Supports linked-list buffer processing
    – 16-DWord Tx DMA FIFO
    – 16-DWord Rx DMA FIFO
    – 4-DWord burst of Rx descriptors
    – 3-DWord burst of Tx descriptors
    – n-DWord burst of configuration blocks (n is unlimited according the MUNICH128X, but internal port arbitration may lead to a lower typical burst size of 4 or 8 DWords)
• Dynamic Programmable Channel Allocation
    – Compatible with T1/DS1 24-channel and CEPT 32-channel PCM byte format
    – Concatenation of any, not necessarily consecutive, time slots to superchannels independently for receive and transmit direction
    – Support of H0, H11, H12 ISDN-channels
    – Subchanneling on each time slot possible

• Bit Processor Functions (adjustable for each channel)
    – HDLC Protocol
        – Automatic flag detection
        – Shared opening and closing flag
        – Detection of interframe-time-fill change, generation of interframe-time-fill ‘1’s or flags
        – Zero bit insertion
        – Flag stuffing and flag adjustment for rate adaption
        – CRC generation and checking (16 or 32 bits)
        – Transparent CRC option per channel and/or per message
        – Error detection (abort, long frame, CRC error, 2 categories of short frames, non-octet frame content)
        – ABORT/IDLE flag generation
    – V.110/X.30 Protocol
        – Automatic synchronization in receive direction, automatic generation of the synchronization pattern in transmit direction
        – E/S/X bits freely programmable in transmit direction, may be changed during transmission; changes monitored and reported in receive direction
        – Generation/detection of loss of synchronism
        – Bit framing with network data rates from 600 bit/s up to 38.4 Kbit/s
    – Transparent Mode A
        – Slot synchronous transparent transmission/reception without frame structure
        – Flag generation, flag stuffing, flag extraction, flag generation in the abort case with programmable flag
        – Synchronized data transfer for fractional T1/PRI channels
    – Transparent Mode B
        – Transparent transmission/reception in frames delimited by 00H flags
        – Shared opening and closing flag
        – Flag stuffing, flag detection, flag generation in the abort case
        – Error detection (non octet frame content, short frame, long frame)
    – Transparent Mode R
        – Transparent transmission/reception with GSM 08.60 frame structure
        – Automatic 0000H flag generation/detection
        – Support of 40, 391/2, 401/2 octet frames
        – Error detection (non octet frame contents, short frame, long frame)
    – Protocol Independent
        – Channel inversion (data, flags, IDLE code)
        – Format conventions as in CCITT Q.921 § 2.8
        – Data over- and underflow detected
• 32 Bit / 33 MHz PCI 2.1 Interface
• 32 Bit / 33 MHz De-multiplexed Bus Interface Option
• 0.5 µm, 3.3 V-Optimized Technology
• 3.3 V I/O Capability with 5.0 V Input Tolerance
• 160-pin MQFP Package