General description
The PCA9508 is a CMOS integrated circuit that supports hot-swap with zero offset and provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) for I2C-bus or SMBus applications. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using the PCA9508 enables the system designer to isolate two halves of a bus for both voltage and capacitance, and perform hot-swap and voltage level translation. Furthermore, the dual supply pins can be powered up in any sequence; when any of the supply pins are unpowered, the 5 V tolerant I/O are high-impedance.

FEATUREs
■ 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of the device
■ Supports offset-free hot-swap with IDLE/STOP detect circuitry
■ Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V
■ Footprint and functional replacement for PCA9515, PCA9515A, PCA9517 and PCA9517A
■ I2C-bus and SMBus compatible
■ Active HIGH repeater enable input
■ Static level offset on B side
■ Open-drain input/outputs
■ Lock-up free operation
■ Supports arbitration and clock stretching across the repeater
■ Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters
■ Powered-off high-impedance I2C-bus pins
■ A side operating supply voltage range of 0.9 V to 5.5 V
■ B side operating supply voltage range of 2.7 V to 5.5 V
■ 5 V tolerant I2C-bus and enable pins
■ 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater).
■ ESD protection exceeds 6000 V HBM per JESD22-A114, 450 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
■ Packages offered: SO8 and TSSOP8