datasheetbank_Logo
전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크
HOME  >>>  NXP Semiconductors.  >>> NPIC6C596A-Q100 PDF

NPIC6C596A-Q100 데이터시트 - NXP Semiconductors.

NPIC6C596A-Q100 image

부품명
NPIC6C596A-Q100

Other PDF
  no available.

PDF
DOWNLOAD     

page
20 Pages

File Size
1,009.6 kB

제조사
NXP
NXP Semiconductors. NXP

General description
The NPIC6C596A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. To provide additional hold time in cascaded applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS transistors designed for use in systems that require moderate load power such as LEDs. Integrated voltage clamps in the outputs, provide protection against inductive transients. These voltage clamps make the device suitable for power driver applications such as relays, solenoids and other low-current or medium-voltage loads.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.


FEATUREs and benefits
■ Automotive product qualification in accordance with AEC-Q100 (Grade 1)
   ◆ Specified from -40 °C to +85 °C and from -40 °C to +125 °C
■ Wide supply range 2.3 V to 5.5 V
■ Low RDSon
■ Eight Power EDNMOS transistor outputs of 100 mA continuous current
■ 250 mA current limit capability
■ Output clamping voltage 33 V
■ 30 mJ avalanche energy capability
■ Enhanced cascading for multiple stages
■ All registers cleared with single input
■ Low power consumption
■ ESD protection:
   ◆ HBM AEC-Q100-002 revision D exceeds 2500 V
   ◆ CDM AEC-Q100-011 revision B exceeds 1000 V


APPLICATIONs
■ LED sign
■ Graphic status panel
■ Fault status indicator

Page Link's: 1  2  3  4  5  6  7  8  9  10  More Pages 

부품명
상세내역
PDF
제조사
POWER LOGIC 8-BIT SHIFT REGISTER
STMicroelectronics
Power logic 8-bit shift register
STMicroelectronics
8-bit Shift Register
Hitachi -> Renesas Electronics
8-bit Shift Register
Renesas Electronics
8-BIT SHIFT REGISTER ( Rev : 2007 )
Micrel
8-BIT SHIFT REGISTER
Micrel
8-bit Shift Register
Renesas Electronics
8-bit Shift Register
Renesas Electronics
8-Bit Shift Register
Motorola => Freescale
8-BIT SHIFT REGISTER ( Rev : 1999 )
Micrel

Share Link: GO URL

EnglishEnglish Chinese简体中文 Japanese日本語 Russianрусский Spanishespañol

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]