datasheetbank_Logo
전자부품 반도체 검색엔진( 무료 PDF 다운로드 ) - 데이터시트뱅크
HOME  >>>  Zarlink Semiconductor Inc  >>> MT90222 PDF

MT90222 데이터시트 - Zarlink Semiconductor Inc

MT90222 image

부품명
MT90222

Other PDF
  no available.

PDF
DOWNLOAD     

page
155 Pages

File Size
804.7 kB

제조사
ZARLINK
Zarlink Semiconductor Inc ZARLINK

Description
The MT90222/3/4 device is targeted to systems implementing the ATM FORUM Inverse Multiplexing for ATM (IMA version 1.1 and 1.0) or UNI specifications for T1/E1 rates. In the MT90222/3/4 architecture, up to 16 physical and independent serial links can be terminated through the utilization of off-the-shelf, traditional T1/E1/J1 framers/LIUs and DSL chip sets. The MT90222/3/4 device can also provide up to 10 Mb/s per link data rates for unframed serial TDM transmissions for xDSL applications.


FEATUREs
IMA
• Up to 16 T1, E1, J1, DSL links & up to 8 IMA groups with 1 to 16 links/IMA group1
• Supports symmetrical & asymmetrical operation
• CTC (common transmit) & ITC (independent transmit) clocking modes
• Pre-processing of RX ICP (IMA control protocol) cells
• IMA layer & per link statistics and alarms for performance monitoring with MIB support

TC and UNI
• Supports mixed-mode operation: links not assigned to an IMA group can be used in TC mode
• ATM framing using cell delineation
• HEC (header error control) verification & generation, error detection, filler cell filtering (IMA mode) and idle/unassigned cell filtering (TC mode)
• TC layer statistics and error counts i.e. HEC errors with MIB support

Standards Compliant
• ATM Forum - IMA 1.1 (AF-PHY-0086.001) & backwards compatible with IMA 1.0
• ATM Forum - ATM over Fractional T1/E1 (AF-PHY-0130.00)
• ITU G.804 cell mapping & ITU I.432 cell delineation

General
• Supports unframed serial streams up to 10 Mb/s per T1/E1 or DSL link
• Single chip ATM IMA & TC processor
• Versatile TDM interface for most popular T1 or E1 framers and DSL chipsets
• Up to 6 MT90222/3/4 devices can be spanned using a TDM ring supporting 32 links
• Provides 8 & 16-bit UTOPIA Level 1 & 2 compatible MPHY Interface (MT90222/3/4 slaved to ATM device)
• 16-bit microprocessor interface for Intel or Motorola
• JTAG test support
• 2.5 V core, 3.3 V I/O with 5 V tolerant inputs
• 384 pin PGBA with 1.0 mm pitch balls
• MT90222, MT90223 & MT90224 share the same product package and pin-out configuration


APPLICATIONs
Provides cost effective solutions to implement IMA and/or TC functions over T1, E1, J1 or DSL transport facilities in broadband access networks. Typical applications are for trunking or subscriber access in:
• Integrated multi-service access platforms
• Access multiplexers
• Next-generation DLC
• Wireless local loop
• 3G wireless base-stations

Page Link's: 1  2  3  4  5  6  7  8  9  10  More Pages 

부품명
상세내역
PDF
제조사
T1/E1/J1 Single-Chip Transceiver
Maxim Integrated
T1/E1/J1 Single Chip Transceiver
Zarlink Semiconductor Inc
T1/E1/J1 Single-Chip Transceiver
Dallas Semiconductor -> Maxim Integrated
T1/E1/J1 Single Chip Transceiver
Mitel Networks
T1/E1/J1 3.3V Single Chip Transceiver
Mitel Networks
T1/E1/J1 3.3 V Single Chip Transceiver
Zarlink Semiconductor Inc
Combined E1/T1/J1 Transceiver/Framer ( Rev : 2001 )
PMC-Sierra
T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
Dallas Semiconductor -> Maxim Integrated
T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
Maxim Integrated
T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
Maxim Integrated

Share Link: GO URL

EnglishEnglish Chinese简体中文 Japanese日本語 Russianрусский Spanishespañol

All Rights Reserved© datasheetbank.com  [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]