Dual Data Link Controller

    This technical summary gives a brief overview of the ML145488 Dual Data Link Controller. The ML145488 is a two–channel ISDN LAPD controller with an on–chip direct memory access (DMA) controller. It is intended for ISDN terminal and switch applications where one or two channels of data will use HDLC–type protocols. The DDLC can also be used in local area, wide area network, and bridge router applications. Each serial interface can be clocked at data rates upto 10 Mbps. The DDLC can operate with microprocessors using clock frequencies up to 20.5 MHz.

• Two Independent Full–Duplex Bit–Oriented Protocol Controllers Support
   HDLC, SDLC, CCITT X.25, CCITT Q.921 (LAPD), and V.120 at Basic
   and Primary Rates
• Four–Channel On–Chip DMA Controller
   —64 kbyte Address Range with Expansion Control
   —Internal Programmable Wait–State Generator
   —Two Buffer Descriptors for Each Receiver Channel
• Compatible with 68000 and 80186 Bus Structures
   —Non–Multiplexed 16– or 8–Bit Data Bus
   —Frame Sizes up to 4096 bytes
• Bit–Level HDLC Processing Including:
   —Flag Generation/Detection
   —Abort Generation/Detection
   —Zero Insertion/Deletion
   —CRC–CCITT Generation/Checking
   —Residue Bit Handler
• TEI/SAPI Address Comparison
   —Three Address Comparisons
   —Wildcard Bits for Block Comparisons
• Transparent Mode for Codec Compatibility
• Programmable Interrupt Vector Generation
• Two Independent Timers Configurable as a Watchdog Timer
• Flexible Serial Interface with:
   —IDL Interface for Connection to Other ISDN Family Devices
   —Timeslot Interface for Connection to PBX–Type Backplanes
   —Modem Interface for Other Applications
• Supports CCITT Specification 1.460
• Supports DMI Specification 3.1 Modes 0, 1, 2, and 3
• Serial Control Port for ISDN Family Device Control
• Low–Power CMOS with Automatic Power–Down
• Serial Data Rates up to 10 Mbps
• DDLC Master Clock up to 20.5 MHz