MECL PLL Components Dual Modulus Prescaler

   This device is a two–modulus prescaler which will divide by 10 and 11. A MECL–to–MTTL translator is provided to interface directly with the MC12014 Counter Control Logic. In addition, there is a buffered clock input and MECL bias voltage source.

• 550 MHz (÷10/11)
• MECL to MTTL Translator on Chip
• MECL and MTTL Enable Inputs
• 5.0 or –5.2 V Operation*
• Buffered Clock Input — Series Input RC Typ, 20 Ω and 4.0 pF
• VBB Reference Voltage
• 310 Milliwatts (Typ)