4-Bit Parallel-In / Pparallel-Out Shift Register

TheMC14035B 4–bit shift register is constructed with MOS P–channel andN–channel enhancement mode devices in asingle monolithic structure. Itconsists of a 4–stageclocked serial–shift register with synchronous parallelinputs and buffered parallel outputs. The Parallel/Serial (P/S) input
allowsserial–right shifting of data or synchronous parallel loading viainputs DP0thru DP3. The True/Complement (T/C) input determines whether the outputsdisplay the Q or Qoutputs of the flip–flop stages. J–K logic forms the serialinput to the first stage. With the J and K inputs connected together they operate as a serial “D” input.

• 4–Stage Clocked Serial–Shift Operation
• Synchronous Parallel Loading of all Four Stages
• J–K Serial Inputs on First Stage
• Asynchronous True/Complement Control of all Outputs
• Fully Static Operation
• Asynchronous Master Reset
• Data Transfer Occurs on the Positive–Going Clock Transition
• No Limit on Clock Rise and Fall Times
• All Inputs are Buffered
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
  Schottky TTL Load Over the Rated Temperature Range