■ FEATURES
• 0.23 µm Process Technology
• Single 3.0 V read, program and erase
   Minimizes system level power requirements
• Compatible with JEDEC-standards
   Uses same software commands with single-power supply Flash
• Address don’t care during the command sequence
• Industry-standard pinouts
   63-ball FBGA (Package suffix: PBT)
• Minimum 100,000 program/erase cycles
• High performance
   90 ns maximum access time
• Flexible sector architecture
   One hundred twenty-eight 32K word sectors
   Any combination of sectors can be concurrently erased. Also supports full chip erase
• HiddenROM region
   128 word of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
   Factory serialized and protected to provide a secure electronic serial number (ESN)
• Ready/Busy Output (RY/BY)
   Hardware method for detection of program or erase cycle completion
• ACC input pin
   At VACC, increases program performance
• Embedded EraseTM* Algorithms
   Automatically pre-programs and erases the chip or any sector
• Embedded programTM* Algorithms
   Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Automatic sleep mode
   When addresses remain stable, automatically switches themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
   Suspends the erase operation to allow a read data and/or program in another sector within the same device
• Sector group protection
   Hardware method disables any combination of sector groups from program or erase operations
• Sector Group Protection Set function by Extended sector protect command
• Fast Programming Function by Extended Command
• Temporary sector group unprotection
   Temporary sector group unprotection via the RESET pin
   This feature allows code changes in previously locked sectors
• In accordance with CFI (Common Flash Memory Interface)