DESCRIPTION:
The IDT79R3500 RISC Microprocessor consists of three tightly-coupled processors integrated on a single chip. The first processor is a full 32-bit CPU based on RISC (Reduced Instruction Set Computer) principles to achieve a new standard of microprocessor performance. The second processor is a system control coprocessor, called CP0, containing a fully-associative 64-entry TLB (Translation Lookaside Buffer), MMU (Memory Management Unit) and control registers, supporting a 4GB virtual memory subsystem, and a Harvard Architecture Cache Controller achieving a bandwidth of 320MBs/second using industry standard static RAMs. The third processor is the Floating Point Accelerator which performs arithmetic operations on values in floating-point representations. This processor fully conforms to the requirements of ANSI/IEEE Standard 754-1985, “IEEE Standard for Binary Floating-Point Arithmetic.” In addition, the architecture fully supports the standard’s recommendations

FEATURES:
• Efficient Pipelining—The CPU’s 5-stage pipeline design assists in obtaining an execution rate approaching one instruction per cycle. Pipeline stalls and exceptions are handled precisely and efficiently.
• On-Chip Cache Control—The IDT79R3500 provides a high-bandwidth memory interface that handles separate external Instruction and Data Caches ranging in size from 4 to 256kBs each. Both caches are accessed during a single CPU cycle. All cache control is on-chip.
• On-Chip Memory Management Unit—A fully-associative, 64-entry Translation Lookaside Buffer (TLB) provides fast address translation for virtual-to-physical memory mapping of the 4GB virtual address space.
• Dynamically able to switch between Big- and Little- Endian byte ordering conventions.
• Optimizing Compilers are available for C, FORTRAN, Pascal, COBOL, Ada, PL/1 and C++.
• 20 through 40MHz clock rates yield up to 32VUPS sustained throughput.
• Supports independent multi-word block refill of both the instruction and data caches with variable block sizes.
• Supports concurrent refill and execution of instructions.
• Partial word stores executed as read-modify-write.
• 6 external interrupt inputs, 2 software interrupts, with single cycle latency to exception handler routine.
• Flexible multiprocessing support on chip with no impact on uniprocessor designs.
• A single chip integrating the R3000 CPU and R3010 FPA execution units, using the R3000A pinout.
• Software compatible with R3000, R2000 CPUs and R3010, R2010 FPAs.
• TLB disable feature allowing a simple memory model for Embedded Applications.
• Programmable Tag bus width allowing reduced cost cache.
• Hardware Support of Single- and Double-Precision Floating Point Operations that include Add, Subtract, Multiply, Divide, Comparisons, and Conversions.
• Sustained Floating Point Performance of 11 MFlops single precision LINPACK and 7.3MFLOPS double precision
• Supports Full Conformance With IEEE 754-1985 Floating Point Specification
• 64-bit FP operation using sixteen 64-bit data registers
• Military product compliant to MIL-STD 833, class B