Description
The HN29V1G91 series achieves a write speed of 10 Mbytes/sec, which is 5 times faster than Renesass previous multi level cell Flash memory, using 0.13µm process technology and AG-AND (Assist Gate-AND) type Flash memory cell using multi level cell technology provides both the most cost effective solution and high speed programming.

FEATUREs
• On-board single power supply: VCC = 2.7 V to 3.6 V
• Operation Temperature range: Ta = 0 to +70°C
• Memory organization
    - Memory array: (2048+64) bytes × 16384 page × 4 Bank
    - Page size: (2048+64) bytes
    - Block size: (2048+64) bytes × 2 page
    - Page Register: (2048+64) bytes × 4 Bank
• Multi level memory cell
    - 2bit/cell
• Automatic program
    - Page program
    - Multi bank program
    - Cache program
    - 2 page cache program
• Automatic Erase
    - Block Erase
    - Multi Bank Block Erase
• Access time
    - Memory array to register (1st access time): 120 µs max
    - Serial access: 35 ns min
• Low power dissipation
    - Read ICC1 (50 ns cycle): 10 mA (typ)
    - Read ICC2 (35 ns cycle): 15 mA (typ)
    - Program ICC3 (single bank): 10 mA (typ)
    - Program ICC4 (Multi bank): 20 mA (typ)
    - Erase ICC5 (single bank): 10 mA (typ)
    - Erase ICC6 (Multi bank): 15 mA (typ)
    - Standby ISB1 (TTL): 1 mA (max)
    - Standby ISB2 (CMOS): 50 µA (max)
    - Deep Standby ISB3: 5 µA (max)
• Program time: 600 µs (typ) (Single/Multi bank)
    - transfer rate: 10 MB/s (Multi bank)
• Erase time: 650 µs (typ) (Single/Multi bank)
• The following architecture is required for data reliability
    - Error correction: 3 bit error correction per 512byte are recommended.
    - Block replacement: When an error occurs in program page, block replacement including corresponding page should be done. When an error occurs in erase operation, future access to this bad block is prohibited. It is required to manage it creating a table or using another appropriate scheme by the system (Valid blocks: Initial valid blocks for more than 98% per Bank. Replacement blocks must be ensured more than 1.8% of valid blocks per Bank).
    - Wear leveling: Wear leveling is to level Program and Erase cycles in one block in order to reduce the burden for one block and let the device last for long time. Actually, it does detect the block which is erased and rewritten many times and replace it with less accessed block. To secure 105 cycles as the program/erase endurance, need to control not to exceed Program and Erase cycles to one block. You should adopt wear leveling once in 5000 Program and Erase cycles. It is better to program it as a variable by software.
• Program/Erase Endurance: 105 cycles
• Package line up
    - TSOP: TSOP Type-I 48pin package (TFP-48DA)